Are there some tools help one to write testbench(vhdl)?

ddt694 · Mar 7, 2004

Are there some tools help one to write testbench (vhdl)?

in a complex design, write testbench is a very troubling thing.

SphinX · Mar 8, 2004

Hi Guy,

**broken link removed**
**broken link removed**

Try to use google for more.

SphinX

Dongbei · Mar 10, 2004

vera or e is your select! you can get some good information from : verificatoin.com

AlexK · Mar 10, 2004

And one more interesting tool for generating testbenches from timing diagrams:
www.timingtool.com

Ace-X · Mar 10, 2004

One more comes from h**p://www.hightech-td.com/
Looks pretty nice and works for both VHDL and Verilog. Supports formulas. Shareware.

Ace-X.

wasp · Mar 11, 2004

paviljonac · Mar 14, 2004

Xilinx System Generator for simulink can generate vhdl test benches.

csliu · Mar 14, 2004

A good test bench need to emulate CPU interface, all the interface emulation/driver/monitor. That's pretty complicated.