vlsi_freak
Full Member level 2
Verilog State Assignment
Hi All,
In VHDL, we can write same set of logic for multiple states as shown below,
when STATE_A | STATE_B =>
----
-----
How we write an equivalent logic in Verilog.
Please help me.
regards,
freak
Hi All,
In VHDL, we can write same set of logic for multiple states as shown below,
when STATE_A | STATE_B =>
----
-----
How we write an equivalent logic in Verilog.
Please help me.
regards,
freak