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implementing Xilinx CoreGen Floating Point V3.0

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schouten_tjeerd

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xilinx floating point

I can't figure out how to implement the Xilinx CoreGen generated code. I want to do some floating point operations (let's say a division). I am only interested in synthesizing my vhdl code and making the FPGA actually doing something, simulation is not used.

This is what I have found out so far:

-Using ISE WebPack 10.1 generate a core:
-Project->New source->IP (CORE Generator & Architecture Wizard)
-Enter file name and tick "Add to project"
-Math functions->Floating-point v3.0
-Select the divide funtion, single precision, no extra signals
-This adds an *.xco file to the project.
-Select the xco file in the sources window, then expand "CORE Generator" in the "Processes for" window.
-Double click "View HDL Functional Model", this will open the *.vhd file from the core. Some interesting code...

Now allow me be really simple minded to make the point.

I have this code:

Code: 
--/////////////////////////////////////////////////////////////

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.all;

entity testfile is
    Port ( input_vector : in  STD_LOGIC_VECTOR (7 downto 0);
           output_vector : out  STD_LOGIC_VECTOR (7 downto 0));
end testfile;


architecture Behavioral of testfile is
begin
  test_process : process is
  variable temp_int : integer; 
  variable temp_real : real;
  variable temp_real2 : real;  
  
  begin  
    --get the input 
    temp_int := conv_integer(input_vector);  
    temp_real := real(temp_int);
  
    temp_real2 := temp_real / 5.3;
  
    --dump the output
    temp_int := integer(temp_real2);
    output_vector <= std_logic_vector(to_unsigned(temp_int, 8));  
  end process test_process;
end architecture Behavioral;

----/////////////////////////////////////////////////////////////
And it gives me this error:

Operator <DIVIDE> must have constant operands or first operand must be power of 2

I am sure this has to do with me failing to actually link the core in some way to my code. So my question is: how do I do this?
 

coregen floating point

Ok, I found out that I have to place this code in the architecture before "begin:
(from the core generated *.vho file)
Code: 
component float
	port (
	a: IN std_logic_VECTOR(15 downto 0);
	b: IN std_logic_VECTOR(15 downto 0);
	clk: IN std_logic;
	result: OUT std_logic_VECTOR(15 downto 0));
end component;
And this code in the architecture after "begin":
Code: 
your_instance_name : float
		port map (
			a => a,
			b => b,
			clk => clk,
			result => result);
"your_instance_name" can stay the same.
Then place "clk: IN std_logic;" in the entity decleration, and declare the rest as signals:
Code: 
signal	a: std_logic_VECTOR(15 downto 0);
signal	b: std_logic_VECTOR(15 downto 0);
signal	result: std_logic_VECTOR(15 downto 0);

That will synthesize the code. It hogs up quite some resources though...
In any case, the next question is, how can I let the core actually do some useful work on my real numbers, or vectors... I gues that "/" sign still won't work?
 

ise webpack floating point

Ok, here are some new findings:
To get the FPU to work, this needs to be done (I think):

Code: 
  variable vector1_from_SDRAM: std_logic_VECTOR(7 downto 0);
  variable vector2_from_SDRAM: std_logic_VECTOR(7 downto 0);
  variable temp_vector:              std_logic_VECTOR(15 downto 0);
	 
  --copy the 8 bit vector to the floating point format vector
  a(9 downto 2) <= vector1_from_SDRAM;
  b(9 downto 2) <= vector2_from_SDRAM;
		  
  --enable the fpu
  --the clk is already hooked via a port to the clock source
  ce <= '1';
		  
  --wait until the fpu is done.
  while (rdy /= '1') loop
    null;
  end loop; 
		  
  --the fpu is now done, so use the result
  temp_vector := result;

Next question: How can I put this in a nice "function", something like:
temp_vector := divide(a,b);
The problem is that functions cannot access signals... Any ideas?

Thanks.
 

xilinx how to use coregen files

Have you heard about IEEE 754 standard. Please read about it..

https://en.wikipedia.org/wiki/IEEE_floating-point_standard

**broken link removed**

Assume ur going to use a floating point divider u have to represent ur floating point numbers in a binary format and give it as an input to Xilinx CoreGen Floating Point v3.0 for division.

The result would also be normally represented in IEEE 754 floating point representation.
 
floating point xilinx

Thanks, indeed I have to adhere to the floating point format.
Anyway, how can I simplify those operations to make the computation to work (enable the core with ce, wait until it is ready, etc) ?
Like with a function.
 

xilinx floating point core

i was going through datasheet of the Floating Point core V3.0. The core has ports

1> CE: Clock Enable (input port)

2>RDY: Output Ready: Set high by core when RESULT is valid.

u can use these ports for implementing the functionality u want.

Go through the Datasheet of the core for more details. The document no is DS335 of Xilinx.
 

xilinx coregen

Yes indeed, I figured that one out (see my post above). I also found out how to use signals in a function: don't use a function but a procedure. That pretty much solves all these problems.
 

Hi, i guess noe you are pretty much clear about floating point core in xilinx.
I am having a basic problem if you can solve it please reply as soon as possible
I am having 25 bit binary number ( read it clearfully plain binary and not floating point binary) but now i want to divide it with some number. And for that i want to use floating point core avilable with xilinx but i am unable to convert this plain binary number into folating point one
Please help
 

Well, actually I am still not an expert because in the end I decided to do all the floating point stuff on the computer by sending it back and forth via an FTDI USB chip.

I think the best way to do it is to "manually" copy your bits to the appropriate location of the floating point number. Look up the datasheet to see the location of the bits in the floating point and their meaning.

Let me know if it works, 'cause I still have to figure it out too.
 

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