Gate Count Vs Slice Count

fpga gate count

Hi All,

In Fpga's give area report based on number of Slices used by logic.

In Xilinx technology what is the equilant gate count for 1 slice/clb. How can a user predict gate count during FPGA prototyping.

Is slice count same as ALUT count in Altera FPGA.

Please share your thoughts,

regards,
freak

slices to gates

Hi Frek,
Both Xilinx and Altera have different architecture of their basic building blocks. So answer to your question " Is slice count same as ALUT count in @ltera FPGA" is no. Both counts are not same. Some times ALUT is capable of packing more combinational logic than what a single Xilinx Slice can.

If you want to estimate at the time of fpga prototyping ... you can go in this way...
1 Flip Flop = 7-8 gates of ASIC
1 LUT = 5-6 gates
for block RAMS ..memory bits will be remain same for both ASIC and FPGA.
As you might be knowing that all the FPGA tools detailed report mention total number of flops used, total Block RAM (xilinx) or Embedded RAM(altera) used. So you can use this information to estimate the gate count.
Please note that if you use the coding styles suggested by Xilinx, it will optimize the logic such way it get pack in very few slices , which can take huge number of gate count in ASIC. (e.g. shift register using SLR16 coding style in Xilinx)

Hope this helps...