pobi24
Newbie level 4
Please, i need help.
Hi,
I need help in designing a 16-bit Carry-select Adder. Input two 16-bit numbers A & B. Output is 16-bit sum and a carry. Use any adder form and any logic form static, dynamic, or any variation of these or within these families.
You don't have to do the simulation because i just need the layout design and the truth table. But if you want to help me with the simulation using HSPICE, please keep reading.
Performance Measure: Use Area A, Time T, Power P, or AT^2 as the circuit performance.
Testing: Choose an optimum test vestor to test the design.
Noise Margins: You can choose any logic swing. The noise margins should be at least 10% of the voltage swing.
Rise and Fall times: All input signals and clocks have rise and fall times of less than 100 psec. The rise and fall times of the output signals ( 10% 90%) should not exceed 1nsec.
Load capacitance: Each output bit of the comparator should have a 20 fF load.
Thank you in advance.
Hi,
I need help in designing a 16-bit Carry-select Adder. Input two 16-bit numbers A & B. Output is 16-bit sum and a carry. Use any adder form and any logic form static, dynamic, or any variation of these or within these families.
You don't have to do the simulation because i just need the layout design and the truth table. But if you want to help me with the simulation using HSPICE, please keep reading.
Performance Measure: Use Area A, Time T, Power P, or AT^2 as the circuit performance.
Testing: Choose an optimum test vestor to test the design.
Noise Margins: You can choose any logic swing. The noise margins should be at least 10% of the voltage swing.
Rise and Fall times: All input signals and clocks have rise and fall times of less than 100 psec. The rise and fall times of the output signals ( 10% 90%) should not exceed 1nsec.
Load capacitance: Each output bit of the comparator should have a 20 fF load.
Thank you in advance.
