ramzitligue
Member level 1
hi , i have written a vhdl code which its main function is to allow to pass the input to the output only when r_w='1' and when r_w='0' nothing happend but the code didn't work.in fact, i put '1' in r_w then after 100 ns i put '0' but the input still pass to the output
her is the code:
if r_w0 = '1' then
sorrout0 <= entrout0;
addout0 <= addin0;
else
addout0 <= addin0;
end if;
where is the problem please
her is the code:
if r_w0 = '1' then
sorrout0 <= entrout0;
addout0 <= addin0;
else
addout0 <= addin0;
end if;
where is the problem please