danesh
Full Member level 3
vhdl shift register
hi guys,
im newbie in VHDL. i have assignment to write left shifting shift register in dataflow model. here is the code tht i need to change it to dataflow model:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift_register is
port( d:in std_logic_vector (7 downto 0);
ldsh: in std_logic;
en: in std_logic;
w: in std_logic;
clk: in std_logic;
rst: in std_logic;
q : buffer std_logic_vector(7 downto 0));
end shift_register;
architecture shift of shift_register is
begin
process (clk,rst)
begin
if rst= '0' then
q<= (others=>'0');
elsif (clk'event and clk='1') then
if en='1' then
if ldsh='1' then
d(0)<=0;
q<=d;
else
q(0)<=w;
for i in 1 to 7 loop
q(i)<=q(i-1);
end loop;
end if;
end if;
end if;
end process;
end shift;
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hi guys,
im newbie in VHDL. i have assignment to write left shifting shift register in dataflow model. here is the code tht i need to change it to dataflow model:
----------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift_register is
port( d:in std_logic_vector (7 downto 0);
ldsh: in std_logic;
en: in std_logic;
w: in std_logic;
clk: in std_logic;
rst: in std_logic;
q : buffer std_logic_vector(7 downto 0));
end shift_register;
architecture shift of shift_register is
begin
process (clk,rst)
begin
if rst= '0' then
q<= (others=>'0');
elsif (clk'event and clk='1') then
if en='1' then
if ldsh='1' then
d(0)<=0;
q<=d;
else
q(0)<=w;
for i in 1 to 7 loop
q(i)<=q(i-1);
end loop;
end if;
end if;
end if;
end process;
end shift;
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