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Verilog: Declaring port instances

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laserbeak43

laserbeak43

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verilog bidirectional port

Hi,
I'm reading a Verilog book and i'm at a point where i'm learning about port declarations. My problem is, that it looks like the port, q, in the code that i'm looking at seems to be declared twice?

Code: 
module DFF(q, d, clk, reset);
output q;
reg q; // Output port q holds value; therefore it is declared as reg.
input d, clk, reset;
...
...
endmodule

is this legal? do you have to declare q an output before you can declare it a reg?
i thought a reg had to be an output anyway?
 

ok, thanks.
I'll look, cause I need to know why i would need it. along with an output declaration, that is.

Added after 6 minutes:

pini_1 said:
The reg declaration is not related to the out. If your output is combinatoral and is driven by an assign or other module you don't need the reg declaration.

You may want see lots of examples at
Code Download: SDIO Slave code::**broken link removed**
Click to expand...

that link has a virus. My scanner caught it.
**broken link removed**
 

Hi
if your targetting a sequential circuit then the output need to be reg,its not compulsion to be reg...i mean...
 

my question is, why should i declare q as output if i'm going to declare it as reg anyway?

wouldn't that be inefficient to have 2 lines of code saying that q is an output?
 

You may regard it as inefficient, but it's simply required by Verilog specification.

12.3.3 Port declarations

Each port_identifier in a port_expression in the list of ports for the module declaration shall also be declared in the body of the module as one of the following port declarations: input, output, or inout (bidirectional). This is in addition to any other data type declaration for a particular port— for example, a reg or wire.
Click to expand...
 

    laserbeak43

    laserbeak43

    Points: 2
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FvM said:
You may regard it as inefficient, but it's simply required by Verilog specification.

12.3.3 Port declarations

Each port_identifier in a port_expression in the list of ports for the module declaration shall also be declared in the body of the module as one of the following port declarations: input, output, or inout (bidirectional). This is in addition to any other data type declaration for a particular port— for example, a reg or wire.
Click to expand...
Click to expand...
That's the answer i was looking for! thanks!!
where did you find that?
 

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