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Methods for optimizing design for area utilization

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Hello everyone,

Currently I'm working on making my design as small as it is possible.
(smallest achievable LUT count)

I've already tried to achieve this goal using some tricks like conversion from case statement to internal tri-state logic, or mapping logic to BRAM.

Unfortunately results was not satisfying.

Are there any other methods of optimizing design for area utilization?
(based on modifications in HDL source code)

I'm concentrating on Xilinx technology, but I'm also interested in making my design smaller on i.e. Altera or Latice.

Best regards,
Ig0
 

Design optimisation

This Xilinx info may help you. "Area Reduction Strategies":
**broken link removed**

Also search the ISE "Synthesis and Simulation Design Guide" for the words "area" and "optimization". Various tips are scattered throughout that manual.
 

Re: Design optimisation

Hi !

It is quite a large question, and it depends on your application...

If you have some parrallel data flow (filter), you could increase the system clock frequency and multiplex the data flow.

You should reduce counter / fifo / ram to the minimum deep needed.

good luck.
 

Re: Design optimisation

Use synchronous reset in your design. Manually assign the global clock signals using "bufg" buffer. Use all the global clock routings (although all signals are not clock, identify long signal paths and assign them on global clock tree), it will reduce no. of route-through slices in the device.
 

Design optimisation

What if I'm not using XST ? .. my current synthesis tool is Synplify ..
 

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