help in verilog coding

illegal reference to net verilog

Hello friends,

I am facing some problem with the code. I am implementing a algorithm in verilog. The code below i pasted is a butterfly code.


The inputs to the butterfly are 4 words each of 12bits..

The outputs to the butterfly are 4 words each of 14 bits.


`include "adder.v"
module butterfly(row , result);

input [9:0]row[3:0];
output[10:0]result[3:0];

wire [10:0]t[3:0];
wire [11:0]temp_result[3:0];
wire [11:0]temp_input[1:0];

wire [3:0] size;

assign size = 4'b1001;

adder a0(row[0] , row[3] ,size,t[0]); // row[0] + row[3] = t[0]

adder a1(row[1] , row[2] ,size,t[1]); // row[1] + row[2] = t[1]


// 2's complement representation for -row[2] and -row[3].

assign temp_input[0] = (~row[2])+11'b000_0000_0001;
assign temp_input[1] = (~row[3])+11'b000_0000_0001;

adder a2(row[1] , temp_input[0],size,t[2]); //row[1]-row[2] = t[2]

adder a3(row[0] , temp_input[1],size,t[3]); // row[0] - row[3] =t[3]


// The above four adders are used for computing the stage-1
//of the butterfly


// The below adders will perform stage-2 operation

assign size = 4'b1010;

adder a4(t[0] , t[1] , size , temp_result[0]);
assign result = temp_result[0]; // t[0] + t[1] = result[0]

assign temp_input[0] = (~t[1])+11'b0_0000_0001;
adder a5(t[0] ,temp_input[1],size, temp_result[1]);
assign result[2] = temp_result[1]; // t[0] - t[1] = result[2]


assign temp_input[1] = t[3]<<1; // left shifts the t[3] = 2t[3]
adder a6(t[2] , temp_input[1], size , temp_result[0]); // computes the addition
assign result[1] = temp_result[2]; // 2t[3] + t[2] = result[1]

assign temp_input[1] = t[2]<<1; // left shifts the t[2] = 2t[2]

assign temp_input[1] = (~temp_input[1])+11'b0_0000_0001;
//computes the 2's complement of -2t[2]

adder a7(t[3] , temp_input[0], size , temp_result[0]); // computes the addition

assign result[3] = temp_result[3]; // t[3] -2t[2] = result[3]

endmodule


This is the error i got when i run this in model sim


* Error: D:/Integer Transform block/butterfly.v(2): (vlog-2110) Illegal reference to net array "row".
# ** Error: D:/Integer Transform block/butterfly.v(2): (vlog-2110) Illegal reference to net array "result".
# ** Error: D:/Integer Transform block/butterfly.v(39): (vlog-2110) Illegal reference to net array "result".
# ** Error: D:/Integer Transform block/butterfly.v(39): Cannot assign a packed type to an unpacked type


Please explain me how to code for these kind of inputs and outputs


Thanks and Regards
Deepak

cannot assign a packed type to an unpacked type

deepu

to name a few
1. input and output definition do not match your description of 12 and 14 bit;
2. result and row are multi-dimensional array, cannot be used as input/output port
spell them out as result_0, result_1, ... or
define them as packed array, e.g. input [12*4-1:0] row;
3. assign result = temp_result[0];
you assigned a slice of temp_result to the entire multi-dimensional array
4. "size" is assigned twice in your code to different value

hope this help get you started
imon

(vlog-2110) illegal reference to net array

Hi ,

I understood the 1 and 2 points.

But for the 3 point, if we assign result = temp_result[0],
then it is going to store in the result[0],

then what about the other addition results , temp_result[1],temp_result[2],temp_result[3]?

Thanks and Regards
Deepak

Added after 1 minutes:

The size is not getting connected to the size in the adder.

The dimensions of the size in this module and the adder module are same.

Both are of 4 bits wide. But i dont know y it is not getting read by that size in the adder.

cannot assign an unpacked type to a packed type

I simply pointed out that is what the compiler complaint about. Because of array dimension mismatch.
You can do
assign result[0] = temp_result[0];
hope this is helpful.