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How to assign pin in graphics mode for that clk_raw signal?

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senthilkumar

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xilinx pgm help?

hai,

i write the code in ise like this

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity seven_seg is
port (
clk_raw : in std_logic;
a : in std_logic;
b : in std_logic;
c :eek:ut std_logic
);
end seven_seg;


architecture seven_seg_arch of seven_seg is
begin

c<= a and b;

end seven_seg_arch;



after i compile ok

sysntheisis ok

in pin constrin the clkraw will not come

only a b c come

how can i assign pin in graphics mode for that clk_raw signal.


any one help that.

thanks
 

Re: xilinx pgm help?

hi

since u have not use clk_raw it is not seen after synthesis.

try using attribute " keep" for the signal clk_raw...
it will retain the pin after synthesis..

thanks..
 

Re: xilinx pgm help?

If you don't use it why do you want to assign a pin to that signal?

Just trying the tool?

Why do you use the graphic mode? I personally don't like it and don't use it. 8)

--maestor
 

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