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Regardin clock divider virtex 2 pro xcv30

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arunjatti

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Hi all,

Im using a clock divider in virtex 2p , im able to check the clock when implemented in divider module .i.e input is 100Mhz clock output is 1hz clock , but this 1hz clock when im giving to any other module it is showing some prob with skew ettc warning and output is not seen ....

how to divide the clock in Virtex2P (100MHZ) clock to around <1hz a??
and can i give this 1 hz clock to other modules(as in my case its not working)??

thanks in advance
arun
 

I assume you are using a divide-by-100-million counter to generate the 1 Hz signal.
Feed that signal through a global clock buffer such as a BUFG. That should provide a nice low-skew clock throughout the FPGA.
 

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