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VHDL code for ones counter

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vhdl count ones

what is a "ones counter"?
you've a byte input, maybe with a data valid, and you've to see if the data is equal to x"01" and count them?

If yes I hope that you're able to write it cause it's very simple.

if that's the problem you can do something like this:

process(clk,rstn)
if rstn = '0' then
cnt <= (others => '0');
elsif clk'event and clk = '1' then
if datain = x"01" then
cnt <= cnt + 1;
end if;
end if;
end process;

You've to refine it such as resetting counter when it's at its maximum or if you've externa signal, take in account an eventual input_data_valid, put cnt on the output of the block and put a trigger for see it at specifical instants..
 

count 1s in vhdl

one's counter is that which coutns number of one's in a string....e.g. in "001110' there are three one's.

My instructor has given hint that:
make Multiplexure; Adder; clock and then call them
 

vhdl count number of 1

Checkout this one ....
Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.arith.all;

entity ones_count is
  
  port (
    clk     : in  std_logic;
    rst_n   : in  std_logic;
    ld_data : in  std_logic;
    busy    : out std_logic;
    data_in : in  std_logic_vector(7 downto 0);
    count   : out std_logic_vector(3 downto 0));

end ones_count;

architecture behave of ones_count is
signal data : std_logic_vector(7 downto 0);
signal count_i : std_logic_vector(2 downto 0);
signal sum : std_logic_vector(3 downto 0);
begin  -- behave
  count <= sum;
  process (clk, rst_n)
  begin  -- process
    if rst_n = '0' then                 -- asynchronous reset (active low)
      data <= (others => '0');
      count_i <= (others => '0');
      busy <= '0';
      sum <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      if ld_data = '1' then
        data <= data_in;
        count_i <= (others => '0');
        busy <= '1';
      end if;
      if count_i /= "111" then
        count_i <= count_i + "001";
        sum <= sum + data(count_i);
      end if;
      if count_i = "111" then
        sum <= sum + data(count_i);
        busy <= '0';
      end if;
    end if;
  end process;

end behave;

-- 
--          __     __     __     __     __     __     __     __     __     __     __    
-- CLK    _/  \___/  \___/  \___/  \___/  \___/  \___/  \___/  \___/  \___/  \___/  \__
--              _______________________________________________________________________
-- RST_N  _____/
--                      ______
-- LD_DATA_____________/      \________________________________________________________
-- 
--        _____________________________________________________________________________
-- DATA_IN___________AA___________________AA________________AA____________AA___________
--            
--                        ______________________________________________________
-- BUSY   _______________/                                                      \______
--        ______________________ ______ ______ ______ ______ ______ ______ ____________  
-- COUNT_i___________0__________X__1___X__2___X__3___X__4___X__5___X__6___X__7_____7___    
--            
--        ______________________ ______ ______ ______ ______ ______ ______ ______ _____  
-- COUNT  ___________0__________X__0___X__1___X__1___X__2___X__2___X__3___X__3___X_4___    
--
 

count number of ones, vhdl

That seems like doing it the hard way.
I don't know VHDL, but in Verilog I would try something like this (the input is an 8-bit signal instead of a string):
Code: 
module top (x, ones);
  input   [7:0] x;
  output  [3:0] ones;

  assign ones = x[7] + x[6] + x[5] + x[4] + x[3] + x[2] + x[1] + x[0];
endmodule
That synthesizes smaller than you might expect. About a dozen simple LUTs in Xilinx ISE.
 

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