Problem with assignment syntax in VHDL

hdlparsers:800

Colleague,

I’m learning VHDL by modifying cookbook examples. I’m using Xilinx WebPack and I have a problem within the following code:


Here’s the error message:

Why am I getting this error? Why can’t I assign a constant (a zero) to a variable? What would be the best solution?

Thanks,
- Nick

vhdl unsigned assignment

try
unsigned as well as std_logic_vector and std_ulogic_vector behave in a manner that you can add some integer to them but you can't assign an integer, by writing (others => '0') you say that all bits of your signal are to be assigned as '0'

for loop syntax in vhdl

firefoxPL said:

try

Code:

wdt_clk_cnt <= (others => '0');

unsigned as well as std_logic_vector and std_ulogic_vector behave in a manner that you can add some integer to them but you can't assign an integer, by writing (others => '0') you say that all bits of your signal are to be assigned as '0'

Click to expand...

Thank you! Your solution worked. Is there a place on the web where somebody with reasonable EECS background (mostly C/C++, microcontrollers and sensors) could look for this type of information?

vhdl reference manual

I started with quite similar programming background and one of the things that I learned is not to think like a c++ programmer, you need to learn basics of digital circuits, after you understand how digital circuits work you will be able to write much better VHDL codes, apart from that keep learning from some vhdl books and you should be all right

vhdl assignment problem

I basically agree with FireFoxPl. One thing is to know the HDL syntax, types and operators defined in the standard packages, that's almost easy to my opinion, the other is to understand the requirements of (mostly) synchronous logic and parallel processing.

It's very helpful, if you have designed digital hardware logic before. Than you are not at risk e. g. to write a VHDL for loop, wondering why the output isn't toggling. This is likely to happen when you approach HDL from the software side.

Learning from cookbook examples isn't bad, generally. It's also good, to have a detailed VHDL reference at hand. I finally stopped at the Synopsys VHDL Reference Manual. Xilinx has copied part of it in their manuals.


Some VHDL constructs are even missing in the Synopsys manual, e. g. using variables in generate statements. The IEEE VHDL standard, present at EDAboard, is the only complete reference, although not a convenient literature.