barath_87
Full Member level 3
fifo ip core
I generated fifo core using xilinx ip core gen.. synthesis was done but while simulating in the same found a
"warning : HDLParsers:3583 - File "J:/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/fifo_generator_v3_3.vhd" which file "C:/Xilinx92i/medianfilter/fifo_128x8x.vhd" depends on is modified, but has not been compiled. You may need to compile "
should i add the ip anywhere else .....
How to simulate the module with ip core.....
Thank you in advance .....
I generated fifo core using xilinx ip core gen.. synthesis was done but while simulating in the same found a
"warning : HDLParsers:3583 - File "J:/J.36/env/Databases/ip/export/rtf/vhdl/src/XilinxCoreLib/fifo_generator_v3_3.vhd" which file "C:/Xilinx92i/medianfilter/fifo_128x8x.vhd" depends on is modified, but has not been compiled. You may need to compile "
should i add the ip anywhere else .....
How to simulate the module with ip core.....
Thank you in advance .....
