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vhdl code for small module

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anoop12

anoop12

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This is a small module.

The inputs are
1) address(1:0)
2) rst1,rst2,rst3
and outputs are
en1,en2,en3.

If address is "00 then en1='1'
If address is "01 then en2='1'
If address is "10 then en3='1'

if rst1='1' then en1='0'
if rst2='1' then en2='0'
if rst3='1' then en3='0'


can anyone provide vhdl code for this?
 

you did not state which condition is priority....

for eg: when address = "00" and rst1 = '1', what is en1??
 

Code: 
process (rst1, rst2, rst3, addr) is begin
  if(rst1 = '1')then
    en1_tmp <= '0';
  elsif(addr = "00")then
    en1_tmp <= '1';
  else
    en1_tmp <= en1_tmp;
  end if;
 if(rst2 = '1')then
    en2_tmp <= '0';
  elsif(addr = "01")then
    en2_tmp <= '1';
  else
    en2_tmp <= en2_tmp;
  end if;
 if(rst3 = '1')then
    en3_tmp <= '0';
  elsif(addr = "10")then
    en3_tmp <= '1';
  else
    en3_tmp <= en3_tmp;
  end if;
end process;

en1 <= en1_tmp;
en2 <= en2_tmp;
en3 <= en3_tmp;
this should do the trick
 

The code reflects the definition, assuming that rstx are intended to have priority (I would also assume this). I wonder however, if the latching operation is actually intended. Also , if a transition from addr = "01" to addr ="10" occurs, the addr = "00" action may be also triggered (and latched until reset) as well due to glitches. At least this behaviour seems to be unwanted and makes me doubt the logic definition.
 

I wonder however, if the latching operation is actually intended.
Click to expand...
Firstly I decided not to use latching, but after a while I edited the code and put the latches intentionally.
 

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