Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
do u know how many test inputs will come for 2 * 2 multiplier? 16 combinations. Then for 8 bit multiplier... Very large number...It will take u many days to write all the cases without missing..
The best way is to do the random test bench... use $random(f) function
deepu,
thatz the reason i am asking for some way to write a code which will test all cases.
Will $random work in VHDL?? I am working on VHDL of Modelsim.
I know that in Verilog you can run a for loop to generate all the cases but in the case of VHDL i am not sure if we can do...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.