How to do GLS simulation ?

I want to do GLS(Gate Level simulation). I have DC-Synthesised netlist and the target library. I need some tutorial on how to do GLS...

gls simulator

Hi,

GLS can be done in following two ways:

1. Zero-Delay simulation: For this you need to make sure that you have compiled all the cells without delay information. Apart from that you need to specify in your simulator to neglect timing checks. This simulation will just be like your RTL simulations but with gate level netlist.
2. With timing: This is little complex case. In this case you need to specify the timing information as well (SDF is most common format). You need to make sure timing information is annotated properly with design. You also need to disable timing checks on synchronizers. This should only be run when the design is clean in STA.

I know this is too little an information for such a general question. If you have any specific questions please do reply back.

Regards,
Achin

Re: GLS Simulation

please upload the tutorial i badly need it.

Re: GLS Simulation

In fact, you need the sdf to do the real GLS !

Re: GLS Simulation

Hi,

You can find out the post "Need for GLS" in my blogspot.

https://chipverification.blogspot.com/search/label/Gate level simulation

Suresh

Re: GLS Simulation

Thanks Suresh with good information from your blog, keep up the good works!