BlackOps
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Hello, i have a design of asynchronous FIFO. FIFO.vhd file contains structural interconnection of its elements. including Counter. The declaration of counter is in the file named FifoParts.vhd ... i compile it good without errors and also successfully simulate in Modelsim.
but when i put this design, and add it all as peripheral in EDK. i get the following errors:
but the declaration of Counter element...and its instantiation is same... what do u think the problem is?
thanks
Added after 1 hours 40 minutes:
the Xilinx answers records give me this:
but the declaration and instantiation DOES match in my design... instantiation of Counter occurs inside FIFO.vhd, and the declaration of Counter is in FifoParts.vhd the oepration of Counter is behavioral code in counter.vhd
and the FIFO is isntantiated in the Top.vhd file.
any ideas?
but when i put this design, and add it all as peripheral in EDK. i get the following errors:
Code:
IPNAME:video_ctrl_0_wrapper INSTANCE:video_ctrl_0 -
E:\PROJECTS\EDK\test18\system.mhs line 161 - Running XST synthesis
ERROR:Xst:2585 - Port <clock> of instance <wcnt> does not exist in definition <Counter>.
ERROR:Xst:2585 - Port <cnt_ena> of instance <wcnt> does not exist in definition <Counter>.
ERROR:Xst:2585 - Port <count> of instance <wcnt> does not exist in definition <Counter>.
ERROR:Xst:2585 - Port <reset> of instance <wcnt> does not exist in definition <Counter>.
ERROR:Xst:2585 - Port <sclr> of instance <wcnt> does not exist in definition <Counter>.
ERROR:MDT - Aborting XST flow execution...
INFO:MDT - Refer to
E:\PROJECTS\EDK\test18\synthesis\video_ctrl_0_wrapper_xst.srp for details
ERROR:MDT - platgen failed with errors!
make: *** [implementation/video_ctrl_0_wrapper.ngc] Error 2
Done!but the declaration of Counter element...and its instantiation is same... what do u think the problem is?
thanks
Added after 1 hours 40 minutes:
the Xilinx answers records give me this:
Code:
Description
Keywords: VHDL, HDLParsers, parse
When I analyze a VHDL design, the following error occurs:
"ERROR:Xst:2585 Port <port_name> of instance <inst_name> does not exist in definition <def_name>"
Solution
Compare the component declaration and instantiation to the submodule that is instantiated. When this error occurs, the declaration matches the instantiation, but it does not match the port declarations of the submodule.
To solve this problem, change either the port declarations in the declaration/instantiation pair or the submodule port declarations so that the two match. This error is specific to the quantity and names of the ports in the submodule.but the declaration and instantiation DOES match in my design... instantiation of Counter occurs inside FIFO.vhd, and the declaration of Counter is in FifoParts.vhd the oepration of Counter is behavioral code in counter.vhd
and the FIFO is isntantiated in the Top.vhd file.
any ideas?
