Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

need a simple source code

Status
Not open for further replies.
farrokhiyan

farrokhiyan

Junior Member level 3
Joined
Sep 17, 2007
Messages
29
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,283
Activity points
1,473
Hi all,
I'm a beginner in vhdl. i need a simple source code for digital integrator in vhdl which is synthesizable on FPGA. can you help me?

tnx.
 

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity signed_integ is
  generic
  (
    DATA_WIDTH : natural := 8
  );
  port 
  (
    clk    : in std_logic;
    reset : in std_logic;
    a       :  in signed	((DATA_WIDTH-1) downto 0);
    result : buffer signed ((DATA_WIDTH-1) downto 0)
  );
end entity;

architecture rtl of signed_integ is
begin
  process (clk,reset)
  begin
    if reset = '1' then
      result <= (others => '0');
    elsif rising_edge(clk) then	
      result <= result + a;
    end if;	
  end process;
end rtl;
 

    farrokhiyan

    farrokhiyan

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top