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VHDL code for quadrature NCO

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missbirdie

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vhdl+cpld+quadrature

Hello I am new to VHDL so i really need help

I have a Spartan-3A FPGA & I need to implement DUC (Digital up converter) & DDC (Digital Down Converter).. I am having a problem in designing quadrature nco or dds considering dithering.

Can anyone help me with the VHDl code for quadrature NCO ??
Does it have to be LUT ?? or is it better to use the cordic algorithm ??

Thanks alot
 

quadrature down converter fpga

LUT based NCO is the fast and usual way. If I remember right, several NCO examples have been posted within the last month's.
 

sine rom vhdl code

yes i checked them all but none of them was using the cordic algorithm.. I just wanna know the difference .. & how each way affects the FPGA.
Besides if i have a code that generates only Sin & I need a cos signal too what can i do ??? is it just an integration process ???
thanks again
 

lut-based nco

I assume, that you'll use a LUT NCO. For full clock rate, you can utilize a dual port ROM to have sine ans cosine in parallel, for reduced clock rate, the ROM can be multiplexed.
 

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    missbirdie

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vhdl code for phase shift

As i told u i'm new to vhdl and FPGAs..actually this is my 1st code :) so what do u mean by a dual part ROM ??? do i have to get a separate ROM ?? or the memory with the Spartan-3A FPGA kit is enough ??? I need great data rate by the way.
 

vhdl code for cosine

The internal memory blocks of FPGA are generally capable of dual port operation, also with Xilinx Spartan, as far as I know. That means you have one sine ROM, e. g. for one quadrant and can access it at two ports, using different addresses and getting different data output for I and Q. You can use a single phase accumulator that is decoded twice to the ROM addresses, with a 90° offset for the Q part.In some applications, a variable phase shift for the second output may be suitable.
 
phase shifter vhdl code

is it the same idea in both DUC & DDC ?? & how does the data rate affect the design ??
 

digital phase shifter vhdl code

When NCO uses data rate == design main clock, the LUT can't be multiplexed, you need dual port ROM.
 

what do u mean by dual port ROM ?? is it avaialable in Spartan 3A FPGA ???
 

I'm not using Xilinx, but I've seen dual-port memory blocks with Spartan FPGA.
 

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