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two clock frequency operation

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rajsrikanth

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hi
i have to code in my FPGA for two clock frequency operation
ie., iam getting samples at 1MHz frequency and then i have to send the same samples out again in 0.5MHz frequency
i want suggessions on this and iam struck here.


regards
srikanth
 

Can you control the flow of incoming samples, if yes than you can easily buffer the incoming samples in FIFO, if you're using Xilinx FPGA the built-in blockRAM can build dual port FIFO and each port can be clocked by different frequency, only problem is that you will have more incoming samples than outgoing, so if you can stop the incoming samples than you just use FIFO_full signal from generated FIFO to control the flow of incoming samples
 

Well, I suggest that if you could have a control like "HOLD" or "RDY" at the 1MHz data transmitter unit, then you don't might need the FIFO build ups, infact a couple of registers\buffers do the job the best and I have already done it even under async clock devices....However using FIFO logic increases your future expansion, say you can connect even high speed devices with just HOLD or RDY controls....UP Conversion or DOWN conversion is not a big issue unless you have a master as your tx or Rx device...If u need more info,describe your critical part and let's see what v could do...
Regards
 

based upon what i understood, try to use clocking components (e.g. Xilinx DCM components or Altera DLL components).
 

I don't see much sense in guessing about solutions for an uncompletely defined problem. Obviously an input stream can't be repeated continously at a different sample rate, this can be a time limited operation only. So please give a complete problem description.
 

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