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division in verilog - ok in sumilation, error if synthesized

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nidahas

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verilog division

hi!!

i a writing a code in verilog which involves the use of division operator.the code works fine if i check it for syntax or for simulation purposes but gives an error if i synthesize it.it says tha division operatation cannot be done.

i f somebdy can guide me how to go about division.

any help is appreciated.

thanks
 

division in verilog

hardware implementation of division if not done by some IPCore (or small uC) can only be done with dividend which is multiple of 2, so unless yout perform something like
Code: 
signalOut = signalIn/4;
it probably won't work
 

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    nidahas

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Re: division in verilog

Unlike other function blocks, e. g. multiplier, divider are generally not inferred from HDL with usual compiler tools. Parallel dividers, as usually provided as parameterisable modules by FPGA vendors, are performing a division immediately or within one clock cycle, but are consuming a lot of logic cells. Alternatively, serial dividers can do it with less effort, requiring one clock cycle per output bit.
 

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    nidahas

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Re: division in verilog

my dividend is basically a variable......i.e it is varying between 50 to 255
 

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