Migration from Altera to Xilinx

ahdl2hdl

Hi!
How to convert Altera project to Xilinx?
Altera project has complex hierarchical structure made on Quartus for EP2A15 chip . The target Xilinx device is XC2V2000.
What tools i need to do it?
Thanks

library lpm xilinx

Hi,

If your project is written in vhdl, with no specific @ltera macrofunction, you just need to create a new project with ISE, select your virtex 2 device, add your vhdl source files and run the synthesis, map and route.
The hierarchical structure will be redone from your component port map in the vhdl source...

:fadein:

xilinx coregen modules altera

The problem is that Altera project has block diagram (graphic) file as top hierarchy of the project. Other project files are connected to this top BDE file. These files are Verilog, or BDE (graphic) files that contain LPM's. The structure is very complex and confusing.
I'd like to avoid whole project retyping in Verilog, its a lot of work (and new bugs). I wonder if there is no any automatic or semiautomatic way to migrate from Altera to Xilinx.

migratin from altera to xilinx

Ask Xilinx :agrue:

They should help with this, although the amount of effort they put is proportional to the number of the 2V2000 you'll need

I have done things like that in the past but from HDL with some Altera macros to Xilinx, it was OK but if you have schematics...it gets more and more difficult,

good luck,

-maestor

recommended project structure xilinx

For the graphical blocks, did you try the Qu@rtus tool : Create HDL File for current file ... ?

This will help you tho create the top level.
For the macrofunction, it's harder...
:roll:

using xilinx netlist for altera

maestor
I have asked Xilinx, they advice to use AHDL2HDL utility, but it does not help me to convert whole project.

r_e_m_y
Yesterday evening i arrived at a conclusion that this is only way to make a migration. I think the scenario should be:
- Load the project in Quartus and compile it;
- Archive compiled project and then extract the Archive in other directory. This directory will contain all files of the project (include LPMs);
- For every graphic file in this directory: Open *.bdf -> Create project -> Create HDL design file from curreng graphic;
- For Verilog files - nothing to do;
- For LPMs files - rewrite them in Verilog manually. 8O
It would be good, if somebody could advise me a library with Altera's LPMs converted to Verilog or VHDL.
- Finally i build a directory contains only Verilog files, define the top of hierarchy and compile it in Xilinx ISE. ISE should rebuild all project structure automaticaly.

Thanks for advice!

xilinx altera migration

It seems that you are almost there!

This X!linx guys, always keen to help!
Although I have to say that I am a X!linx supporter, probably because most of our costumers are...

-good luck

include altera library in xilinx

It is definately not going to be a simple click and convert with one button.
But having said that, you can still make your job a lot easier.

First get your design converted to VHDL using the Altera tools. And I hope you have a synthesis tool like synplify or leonardo. You dont need to rewrite you altera LPMs. Chances are Xilinx will have something similar in the coregen. You may have to modify your design a little. And you are targeting big part, I hope that the Altera design was a good one to start with. Good idea to refer to the Design Reuse Manual for future designs. You never know when you will have to change the technology.

Anyways welcome to the Xilinx world You will like it.

Kode

ise device migration

xfpgas
Ok, lets say i already have my project as collection of Verilog modules that include LPMs. Then i run synplify in order to convert LPMs to Xilinx libraries. May you explane this point in detail? I mean, how to convert Altera libraries to Xilinx libraries using synplify?

altera to xilinx conversion utility

verilogsh said:

xfpgas
Ok, lets say i already have my project as collection of Verilog modules that include LPMs. Then i run synplify in order to convert LPMs to Xilinx libraries. May you explane this point in detail? I mean, how to convert @ltera libraries to Xilinx libraries using synplify?

Click to expand...

No, Synplify will not convert the LPMs. You can replace those LPMs with
XIlinx Cores from Coregen. Coregen is a tool that generates IP cores - like FIFOs, FFT, etc that are optimized for Xilinx Tehnology Architecture. For example lets say you had a FIFO LPM that you are using in your current design. You can look at the FIFO generated from Coregen and see how it matches with your current design. Like I said, you may have to do some changes for y our design. I would say first look at your LPMs, and go to Xiinx Coregen, and see if you have those available in Xilinx. If you do have them available, you can generate the IP Core, and instantiate that as a module in your design, replacing the Altera LPM. XIlinx wil give you a instanatiation module along with the edf netlist and a datasheet for each core. And ofcourse the ports are not gona be the same names and all...and even you may not have all that you need for your design.

So finally, its a good idea to see if there are any IP cores avaiable in XIlinx COregen, before you start writing your own. I would bet you will find most of what you need, with minor modifications to get them to work with your design.

Hope this helps
Kode

what is xilinx .bde file

xfpgas
Thank you for the explanation.
I'll check Coregen, i think it will no problems with finding library equivalents.
Thanks for help!

lpm library error in ise xilinx

That is the great value of the VHDL !!!

xilinx synthesis using a coregen design

:idea: Another way to make a conversion has been found.

:idea:
Idea:
I can generate ATOM netlist by Quartus (Altera). This netlist is a VerilogHDL module that contains configurations and interconnections of ALL LCELLs (logic cells) used in project. But the LCELL in this module used as a black-box. Adding a “filling” of this black-box will turn the ATOM netlist to a hardware independent VerilogHDL module.
The question is: where can I find a library of Altera LCELLs, I mean HDL description of logic cell. Or may be some datasheet with detailed description of LCELL (apexii_lcell), then I’ll build it by myself (Altera datasheet do not contain enough info).

xilinx lpm library

it will help you tho estilabsh the top level