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Please clear my doubts

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deepu_s_s

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clear the doubts

Hello Friends,

I am having two doubts

1) is there anyway to design 16-bit adder without for loop?
2) I want to use this adder in the multiplier. How can i use this design unit in the multiplier block? Shall i use 'include and instantiate the adder?

Thanks and Regards
Deepak
 

In Verilog or VHDL, simply use the '+' operator. It works with signals having any number of bits.
 

in VHDL you can write a procedure in a package for adder and then you can call it as concurrent or sequential statement whatever you want in multiplier.....
i did not under stand that how are you designing adder using for loop...
 

I am attaching the verilog file of my Carry Save Adder desing

Please have a look at that and do any corrections if required


module csa(a,b,sum,carry);

input [15:0]a,b;

output [15:0]sum;
reg [15:0]sum;

output carry;
reg carry;

reg[15:0] temp_sum,temp_carry;
reg [16:0]sum_temp,carry_temp;
integer i;


always @(a or b)
begin
for(i=0;i<=15;i=i+1)
begin
temp_sum =a ^ b;
temp_carry =a & b;
end
carry_temp = {temp_carry , 1'b0};
sum_temp = {1'b0 ,temp_sum};
sum_temp = sum_temp + carry_temp;
sum =sum_temp[15:0];
carry =sum_temp[16];
end
endmodule
 

Your code seems correct, however Xilinx ISE synthesizes the '+' operator more efficiently:
Code: 
module top(a,b,sum,carry);
  input  [15:0] a, b;
  output        carry;
  output [15:0] sum;

  assign {carry,sum} = a+b;
endmodule
Of course, different tools may synthesize more or less efficiently.
 

Hi echo,
Can we do this using pipeline technique?

Added after 12 minutes:

and one more doubt....

I had written code for CSA in one file and I want to use those CSA in the multiplier module...

How can i use the adders in multplier module? shall i instantiate the adder?

Added after 2 hours 11 minutes:

I have got one more doubt...Please help me with this

Consider 16 bit multiplier... So the result must be a 32 bit wide. I am using wallace tree multiplier.

In that,the final stage will get two outputs carry and sum... those two are given to CPA. My doubt is what will be the width of the inputs at the CPA. Are they will be 16 bit or 32 bit wide?

I am also attaching the supporting document . I am designing with reference to that model

Thanks and Regards
Deepak

Added after 1 minutes:

This is the doc.
 

If the 16-bit adder is too slow for your clock rate, then you could split it into two or more sections and pipeline them.

If you want to use one module inside of another module, yes, you instantiate it. That's how module hierarchy works.

I don't know much about multiplier design, sorry. I usually use the '*' operator, and let the synthesis tools build the multiplier, or use an FPGA multiplier block.
 

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