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what is the benefit of unsynthesizable code?

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unsynthesizable

Dear,
Some codes in VHDL are unsynthesizable. As i understand we can't apply on FPGA or CPLD. So what is the benefit of it?
thanks.
 

unsynthesizable code

HDL can also be used as a modeling tool, in fact it should be used (or a replacement of it) before the design phase.
This can be extremely helpful when estimating the complexity of your design and trying to foresee potential problems.

Actually to know how to write efficiently good non-synthesizable HDL code is a very hard thing to do. This is important for large scale mixed signal projects when one needs to model the analog blocks for example - then execution time can be critical if the modeling is not done right.

ND.
https://asicdigitaldesign.wordpress.com/
 

Unsynthesizable VHDL code in a test bench can be very simple. I'm testing e. g. the digital communication channel of a design. I can test against the code of the corresponding device (if I have designed it also). But for a realistic test, I have to consider cable delays. For this purspose, I use some line of unsynthesizable code in my testbench, particularly an expression with transport delay. Other examples are variable timing generators to simulate clock frequency differences between a serial transmitter and a receiver. HDL models of digital devices (e .g a DDR2 RAM) from a manufacturer are additional examples.
 

Hi,

Normally timing clause are used to model the associated delay with gates or net, thus it helps in modelling the required functionality of any digital ckt.

regards
 

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