foreign Language Interface with modelsim, system C

hi

can any one give me an idea where Foreign Language interface is used...is it used only for testing purpose or does it support some other pupose...

can anyone aslo explain me where is system C used...since VHDL and Verilog being used widely where do system C come into picture....if it helps during System on chip(SoC) then the tool associalted with system C synthesis is it expensive or cheap...if we compare with other xilinx and altera tools...

can ayone give me rough idea of the cost of system C tools...

thanks..

Foreign language interface (FLI) routines are C programming language functions that provide procedural access to information within Model Technology's HDL simulator, vsim. A user-written application can use these functions to traverse the hierarchy of an HDL design, get information about and set the values of VHDL objects in the design, get information about a simulation, and control (to some extent) a simulation run.

ModelSim's FLI interface is described in detail in the ModelSim FLI Reference. This document is available from the Help menu within ModelSim or in the docs directory of a ModelSim installation.

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As far as i know SystemC is mainly used for design verification. The reason to this is simply the money. Designed circuit are nowadays very large and verification cost rises more rapidly than design costs. SystemC rises verification abstraction layer and reduces verification time. You can compare SystemC and VHDL/Verilog to C and assembler.

New modelsim 5.8 supports SystemC (as well as VHDL and Verilog of course). And it cost xx k$ ( i have no idea )

jhenxl said:

As far as i know SystemC is mainly used for design verification. The reason to this is simply the money. Designed circuit are nowadays very large and verification cost rises more rapidly than design costs. SystemC rises verification abstraction layer and reduces verification time. You can compare SystemC and VHDL/Verilog to C and assembler.

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hi jhenxl

thanks for ur reply..can u plz explain me in detail regarding design verification. how is it different from the verification done using VHDL testbenches ...and how does the verification cost reduce using system C.

i didn't get the techinal term clearly "increases the abstraction layer and reduces the verification time" when comparing with VHDL/verilog testbenches.

the idea which i have...(may be wrong idea)...in system C verification u test the "design code written in C language" ...and if that is not synthesiiable then how it is helpful.....

i am not thinking in terms of a system designer...because my present work is into FPGA department ..and i do only the internal FPGA design and Codign according to the specs given....may be this is what is creating problem in my understanding...

thanks..

hi

anyone to solve my problem...atleast a little idea would serve....

thanks