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help me convert from verilog to vhdl

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dzongo

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hi,
please do help me convert this verilog code to vhdl. i need a vhdl version of this code i found on this same page.than yuo;
Code:
module top (clk, sf_ce0, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);
parameter k = 18;
(* LOC="C9" *) input clk; // synthesis attribute PERIOD clk "50 MHz"
reg [k+8-1:0] count=0;
(* LOC="D16" *) output reg sf_ce0; // high for full LCD access
reg lcd_busy=1;
reg lcd_stb;
reg [5:0] lcd_code;
reg [6:0] lcd_stuff;
(* LOC="L18" *) output reg lcd_rs;
(* LOC="L17" *) output reg lcd_rw;
(* LOC="M15" *) output reg lcd_7;
(* LOC="P17" *) output reg lcd_6;
(* LOC="R16" *) output reg lcd_5;
(* LOC="R15" *) output reg lcd_4;
(* LOC="M18" *) output reg lcd_e;

always @ (posedge clk) begin
count <= count + 1;
sf_ce0 <= 1;
case (count[k+7:k+2])
0: lcd_code <= 6'h03; // power-on initialization
1: lcd_code <= 6'h03;
2: lcd_code <= 6'h03;
3: lcd_code <= 6'h02;
4: lcd_code <= 6'h02; // function set
5: lcd_code <= 6'h08;
6: lcd_code <= 6'h00; // entry mode set
7: lcd_code <= 6'h06;
8: lcd_code <= 6'h00; // display on/off control
9: lcd_code <= 6'h0C;
10: lcd_code <= 6'h00; // display clear
11: lcd_code <= 6'h01;
12: lcd_code <= 6'h24; // H
13: lcd_code <= 6'h28;
14: lcd_code <= 6'h26; // e
15: lcd_code <= 6'h25;
16: lcd_code <= 6'h26; // l
17: lcd_code <= 6'h2C;
18: lcd_code <= 6'h26; // l
19: lcd_code <= 6'h2C;
20: lcd_code <= 6'h26; // o
21: lcd_code <= 6'h2F;
22: lcd_code <= 6'h22; //
23: lcd_code <= 6'h20;
24: lcd_code <= 6'h25; // W
25: lcd_code <= 6'h27;
26: lcd_code <= 6'h26; // o
27: lcd_code <= 6'h2F;
28: lcd_code <= 6'h27; // r
29: lcd_code <= 6'h22;
30: lcd_code <= 6'h26; // l
31: lcd_code <= 6'h2C;
32: lcd_code <= 6'h26; // d
33: lcd_code <= 6'h24;
34: lcd_code <= 6'h22; // !
35: lcd_code <= 6'h21;
default: lcd_code <= 6'h10;
endcase
//if (lcd_rw) // comment-out for repeating display
// lcd_busy <= 0; // comment-out for repeating display
lcd_stb <= ^count[k+1:k+0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
end
endmodule
 

It's very time consuming if you want to manually convert from Verilog code to VHDL. It will be much more efficient if you utilize Design Compiler(SYNOPSYS) or RTLCompiler(CADENCE) , they provide the function for converting the design from Verilog to VHDL netlist and VHDL to Verilog netlist thru write -format [VHDL|Verilog] -output {full_path} .
 

you can use the software xhdl to convert the code from verilog to vhdl or from vhdl to verilog.
 

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