assign statement (Blocking & Non Blocking)

1) Non Blocking Assign

assign a <= b;


2) Blocking Assign

assign a = b;


What is the actual difference between case 1 and case 2?

All the Verilog Coding Standard suggest case 2 as formal way.

Hi kungfu,

Consider a,b,c variables

1) a=b;
b=c;
c=a;

2) a <=b;
b<=c;
c<=a;

case 1 outputs: a---value of b.
b---value of c.
c---value of a.

case 2 outputs: a----value of b or c
b----value of a or c
c----value of b or a

In the first case, the simulator assigns sequentially. One after the other same as C language.

In the second case, the simulator treats the statements concurrently.

Internally all the concurrent statements are compiled sequentially with some min. delay known as delta delay.

We dont know which statement in the second may be executed first. It could be statement1 or 3 or could be 2.

I hope its clear

Thanks and Regards
Deepak

I have never seen anything like this:
assign a <= b;
Isn't that a syntax error?

Perhaps you meant a non-blocking procedural assignment:
a <= b;

This is not a blocking assignment:
assign a = b;
It is a continuous assignment, or perhaps a procedural continuous assignments.

This is a blocking procedural assignment:
a = b;

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