how to constrain these clocks ?

derived clock synplify

hi all,in a design there are 3 clocks,which are clk ,clk1 and clk2. clk is the base clk and is expected to about 40Mhz,clk1 and clk2 are devided clks by clk. clk1 is devided by 2 and clk2 is devided by 4. how can i constrain these clks in synplify . should i constrain them in one group?if i do so,synplify will constrain my clk1 and clk2 with 40Mhz,this is not i want it to do. if i constrain them in the different groups,synplify will treat them as unrelated clks,but they are devided by the same base clk. how constrian them?and should i constrain them with multi_cycle constrains?

i do know how to do now!can you help me ??


thx

xilinx constrain derived clock

hi

by this time u might have found the answer....but then too i would like to share something....
if u r using DLL for deriving clk1 and clk2 then by just constraining the clock inputs of DLL u will able to constrain other clocks aslo...

the result u can find in timing analyser report...u can also constraint seperately each clock in Xilinx ISE tool......in xilinx u can constraint the derived clock w.r.t to base clock in terms of frequency and phase..

Quartus tool aslo aupport that...i think synopis should also support i have not worked with it...

hope it wouild be helpful
:?

ucf derived clock constraint

Hi, john:

Could you share with us how you explictly seperately constraint the derived clock in ISE? I've tried "NET derived_clk period=". The ise doesn't recognize this manner. And it requires that the clk should be on pad. Do you use other statements?

I know it will automatically constraint the derived clock when i put constraint on the base clock. But i want to explicitly tell ISE to put more effort on the derived clock which is a doubled clock.

regards

synplify & derived clock

hi dll_embedded.

NET "clk_1" TNM_NET = "clk_1";
TIMESPEC "TS_clk_1" = PERIOD "clk_1" 20 MHz HIGH 50 %;
NET "clk_2_s" TNM_NET = "clk_2_s";
TIMESPEC "TS_clk_2_s" = PERIOD "clk_2_s" "TS_clk_1" / 2 PHASE + 0 ns;

here the clk_1 is the base clock and clk_2_s is the derived clock...clk_2 is half the frequency of clk_1.here clk_2_s is not in the port its an internal clock.

NET "clkin" TNM_NET = "clkin";
TIMESPEC "TS_clkin" = PERIOD "clkin" 20 MHz HIGH 50 %;
NET "wire_clk90" TNM_NET = "wire_clk90";
TIMESPEC "TS_wire_clk90" = PERIOD "wire_clk90" "TS_clkin" * 2 PHASE + 12.5 ns;

here wire_clk90 is derived clock from clkin..
wire_clk90 is the 90 degree phase shifted by twice the clkin ;

when u use dll for multiplication the derived clk nets doesnot appear in the gui global clock window..u can find the the net name and asisign this constraint..but it is not needed since the same constraint the tool applies for dll outputs u can verify from the place and route report showing all the clock constraints..

this constraint can be used just for testing without actually instantiationg a DLL..and finally when it works fine u can add the dll....otherwise i don't find any use using this constarint for dll outputs..

hope it helps....correct me if i am wrong...

= period ts_clkin * 2

Why not use clk1 and clk2 as a enalbe controller signal and make the clk as system clock?
Thus ,the all chip can use only one clock:clk.

derived clock ucf

homeadd said:

Why not use clk1 and clk2 as a enalbe controller signal and make the clk as system clock?
Thus ,the all chip can use only one clock:clk.

Click to expand...

we can use clk1 and clk2 as en and use clk as system clk..in that case all the operation involving clk1 and clk2 should be enabled as multicycle path for timing ananlyser...
aslo i think it would be better to route enable signal in global routing resources or just duplicate the enable logic whever required...

correct me if i am wrong...

tnm_net for internal signals

Sorry, I have a question,
Why you need to constraine the drived clocks. As it is drived from signal CLK then if you constrain the signal CLK and use DLL to drive the other CLK1 and CLK2 (which is a good design practice to use DLL) the CLK1 and CLK2 will be constrained as a follow to CLK.

synplify derived clock

Al Farouk said:

Sorry, I have a question,
Why you need to constraine the drived clocks. As it is drived from signal CLK then if you constrain the signal CLK and use DLL to drive the other CLK1 and CLK2 (which is a good design practice to use DLL) the CLK1 and CLK2 will be constrained as a follow to CLK.

Click to expand...

i do agree that using DLL is a good design pratice..but although the probability is very less...there can be metastabitlity problem due routing dealys of clock when transferring between the base and the derived clock...and we need to put synchronising ckt..and as i stated before the derived clock does gets constrained by constraining the base ..no need to explicity specify...

correct me if i am wrong

synplify derived clocks

Dear John:

Sorry for the late reply. Follwing your way, I've tried to constrain the derived clock. It really doesn't complain about the statements. But when i
use the 'analyze post-place& route static timing' tools, under the constrained item i specified, it states that 0 item is analyzed. Below is what i did in the ucf file.

#nco_clk is the derived clk from the base. It is 2 times the original.

NET "nco_clk" TNM_NET="nco_clk";
TIMESPEC "TS_nco_clk" = PERIOD "nco_clk" 10.5 ns;

Anything i've written wrong?

regards

dll_embed said:

. Below is what i did in the ucf file.
#nco_clk is the derived clk from the base. It is 2 times the original.
NET "nco_clk" TNM_NET="nco_clk";
TIMESPEC "TS_nco_clk" = PERIOD "nco_clk" 10.5 ns;

Click to expand...

hi
the above ucf statement doesnot relate the derived clock with the base clock...u have explicity specifieded the time period for derived no_clk.

NET "base_clk" TNM_NET = "base_clk";
TIMESPEC "TS_base_clk" = PERIOD "base_clk" 20 MHz HIGH 50 %;
NET "no_clk" TNM_NET = "no_clk";
TIMESPEC "TS_no_clk" = PERIOD "no_clk" "TS_base_clk" * 2 PHASE + 0 ns;

this way derived clock is related to base clock.

But when i use the 'analyze post-place& route static timing' tools, under the constrained item i specified, it states that 0 item is analyzed

Click to expand...

this depends on the usage of the derived clock...there might be no register to register path in the derived clock domain to be analysed...

correct me if i am wrong..