Help me with the code_ parallel to serial converter...

Hi all. This is the vhdl code I have written for parallel to serial converter and its testbench. The testbench output is not changing accordingly. Please can any one tell me what is wrong with the testbench I have written. Please its urgent.

Thanks and regards,
Sharada

*******************************************************************

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity p2s is
port( clk: in std_logic;
rst: in std_logic;
par: in std_logic_vector(7 downto 0);
ser: out std_logic);
end p2s;

architecture behavioral of p2s is

signal q: std_logic_vector(7 downto 0);


begin
--clk<= not clk after 100 ns;

process(clk, rst)
begin
if(rst='1') then q<="00000000";
elsif (clk'event and clk='1') then
q<= '1' & q(7 downto 1);

-- q<= '1' & q(7 downto 1);
end if;
end process;
ser<=q(0);
end behavioral;

********************************************************************
Testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity p2stb is
end p2stb;

architecture behavioral of p2stb is

component p2s
port( clk: in std_logic;
rst: in std_logic;
par: in std_logic_vector(7 downto 0);
ser: out std_logic);
end component;

signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal par: std_logic_vector(7 downto 0) := "00000000";
signal ser: std_logic;

begin

clk<= not clk after 50 ns;

U1: p2s port map(clk=> clk, rst=> rst , par => par, ser=> ser);

process(clk)
begin
rst <= '1';
--wait for 50 ns;
rst <= '0' after 50ns;
par <= "10101010";
end process;

end behavioral;

your parallel to serial code is not right... u did not use PAR input... i think u r getting output 0 ... m i right...first chek ur design code.....

in your code
take any load signal
if load='1' then
q<=par;
is not written do it and then check ....