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Verilog bus help required

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davidgrm

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Hi, just starting out with verilog and need some assistance.....

I have 3 devices each with an 8 bit bus. There is a 2 bit control bus and RW / WR signals. B & C also have a CS pin which should go low when a read or write occurs. I am trying to do the following:

Control bus value:


2'b11 - bus connects A to B; RD/WR controls direction - CS on B goes low
2'b10 - bus connects B to C; RD/WR controls direction - CS on C goes low
2'b01 - bus connects A to C; RD/WR controls direction - CS on C goes low
2'b00 - state not valid - CS on B&C goes hi

There is no clock signal just control lines and 8 bit bus.
Any suggestions would be great

Thanks
 

How about something like this? Beware, I haven't check it thoroughly.
Code: 
module top (control, A, B, C, RD, WR, CS_B, CS_C);
  input   [1:0] control;
  inout   [7:0] A, B, C;
  input         RD, WR;
  output        CS_B, CS_C;

  assign B = (control == 2'b11 && WR) ? A : 8'bz;
  assign A = (control == 2'b11 && RD) ? B : 8'bz;

  assign C = (control == 2'b10 && WR) ? B : 8'bz;
  assign B = (control == 2'b10 && RD) ? C : 8'bz;

  assign C = (control == 2'b01 && WR) ? A : 8'bz;
  assign A = (control == 2'b01 && RD) ? C : 8'bz;

  assign CS_B = ~(control == 2'b11 && (RD || WR));
  assign CS_C = ~((control == 2'b10 || control == 2'b01) && (RD || WR));
endmodule
 

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    davidgrm

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