UDP packet losses after adding modules to the system

hi ,
i am working with a system which read data from a cmos camera and send the data as udp packets.following are the hardware specs .

ov7620 camera module
spartan 3 fpga
lan83c185

for first try i coded following modules and try out to send ethernet packet .

1.Udp packet maker (Mbps_tx)
2.crc32 generator (CRC)

i configure the system with above two modules to transmit sudo packets as fast as possible. the data segment of the packet contains a bytes of which are incremented after each packet send.

this system works which consumes 89% (use task manager) present of the whole capacity of 100MBps with out a single packet drop.(i go through incrementing values in each packets ,captured by ethereal )


then i add following two modules to the system.

3.ov7620 camera input processor
4.dual port ram

i modified the Mbps_tx code to read ram.and transmit each horizontal line of a camera per data line.

when run this system . i found out that the there is a packet drop of 5%-10% per image.

i am dead sure this packet dropping is not due to noise on the Ethernet cable.because it works very well when i use only module 1 and 2.

it occur only when i add 3 and 4 modules. i can see the line drops periodically after
12-15 lines.

i am not find the a solution to this packet dropping.i go through entire verilog code and came to there is no mistakes on the code.


i have attached my codes which synthesized on xilinx ise 8.1 here with.please check and see is there any mistakes.

or a ways over come this problem!

what are the reason above kind of failure!

Thanks a lot!

Regards
dilan