FPGA DESIGN OF ELECTRONIC VOTING SYSTEM

voting system using 7 segments

Design a digital circuit of an electronic voting system that will be used in senate., which consists of 200 members. Each member has two switches, SW1 and SW2. SW1 is used to indicate that the member is present at the session. Each member in attendace turns this switch ON, thus sending a 5V signal to the main podium. When the member is absent, the signal at the podium is 0V. A YES vote, recorded by throwing the second switch, sends 5 V on the line to the podium, and a NO vote puts 0V on the line at the podium.

The output is composed of three single LEDS that indicate the result of the vote, YES, TIE or NO. In addition, three 7-segment LED displays indicate the number of members voting.

The chairman of the senate, who stays at the podium, has one switch, which is used to disable the circuit. When all the members have voted either YES or NO, the chairman of the senate throws the podium switch to ON, which latches the results into the display. Once the switch is thrown ON, further vote changes do not change the results that have been latched into the display.

Any hint to solve this problem.

I have the same problem and i don't knowe how i can design this circuit .
i search in the web but i don't find any thing like that

please if any body can help me smqasim .

I am not expert at VHDL (btw, is digital circuit = VHDL??), but I think I can come with a bit help for the clues from my point of view:

1. Identify ur I/O:
Inputs: (3)
members : SW1, SW2 (2)
chairman : show_result (1)
(maybe an optional RESET can be added?)

Outputs: (10)
LED : YES, NO, TIE (3)
7-segment LED (7)

2. Maybe you need a Finite State Machine to indicate mode of operation during voting:
suggested modes: IDLE, VOTING, RESULT

I will leave the logic and relationships inside the system to you for now. All the best.

thanks shilds but we want buolt this circuit as hardwere (block diagram) not like this program language .
we have hear 200 member . every member send signal as ( 0 or 1) .
you can put D Filp flop to output of every member and take the output of flip flop (Q and Q comp) and put it in NOR gate to all give you ( 1).
after that you need to component to count this signal
( i don't knowe what is this component) and give you the number of voter.

Added after 2 minutes:

you can't use logic in this circuit becouse the number of input is big and you need trouth table have 2^200 state.

oo... sorry for my misunderstanding, it's been some time since I did not come across flip-flop stuffs, I think you might need to search for BCD counter design (count 0~9, instead of counting hex numbers which later need to be converted to decimal form) and how to control 7-segments display using some logic table, then get the component to perform the logic.

There is potential security problem with the intended implementation. How would you make sure that no Senator votes twice or changes his vote.

sorry this reply are craps... i was making mistakes in my statements and thinking.... thousand apologies with that.... ><

anyone knows how to delete post?? I would like to delete this to avoid confusion it might give to veiwers.... thx

childs said:

oo... sorry for my misunderstanding, it's been some time since I did not come across flip-flop stuffs, I think you might need to search for BCD counter design (count 0~9, instead of counting hex numbers which later need to be converted to decimal form) and how to control 7-segments display using some logic table, then get the component to perform the logic.

Click to expand...

Is BCD counter count 1 input at a time sequentially?? If that's the case, I think Demultiplexer will do better than BCD counter for counting purpose. Demultiplexor process all inputs simultaneously, hence the security issue mentioned by Virtual Thread can be solved as well.

I don't understand your idea about demultiplexer
can you explain more ?

**broken link removed**

Sorry, english version under construction!