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Help me make a counter with 2 inputs

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shadeslayer

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i want to make counter which have 2 inputs

one is 4mhz clock
secon is one bit input which keeps on set and reset

at output i want only one bit our


now if my input is low for 12 pulses thn my output shuld go low ,,,


how can i do this???
 

Re: counter help

Hi shadeslayer,

To implement the functionality you described, you can follow the here after steps:

1- Detect the input edges (falling and rising).
2- If a falling edge occurs then start counting, if it's a rising edge then reset the counter.
3- The output is keept 1, until counter reaches 12, then it goes low.

If you need more details on how to detect edges, how the hold the value of output without using a latch, or how to implement the counter, then ask and I will follow with you.

Yours,
Said.
 

counter help

I don't understand the words "keeps on set and reset".

Assuming you want a synchronous design, here's some Verilog.
While 'in' is high, load a 5-bit counter with -12. While 'in' is low, count up until the MSB changes to 0. Output the MSB.
Code: 
module top (clk, in, out);
  input         clk, in;
  reg     [4:0] count = -12;
  output        out;

  assign out = count[4];

  always @ (posedge clk)
    count <= in ? -12 : count + count[4];
endmodule
 

Re: counter help

echo47 ....I am not a verilog guy. But i liked the way you coded above design. Very precise!!
i guess Verilog is very good in making witty one liners.
 

Re: counter help

echo47 said:
I don't understand the words "keeps on set and reset".

Assuming you want a synchronous design, here's some Verilog.
While 'in' is high, load a 5-bit counter with -12. While 'in' is low, count up until the MSB changes to 0. Output the MSB.
Code: 
module top (clk, in, out);
  input         clk, in;
  reg     [4:0] count = -12;
  output        out;

  assign out = count[4];

  always @ (posedge clk)
    count <= in ? -12 : count + count[4];
endmodule
Click to expand...

echo47, what happens when 'in' is not synchrone with 'clk' ? (it comes from outside or from another clock domain)
 

counter help

If 'in' is not synchronous with 'clk', then my counter example could malfunction due to setup/hold violation of the counter flip-flops. One simple remedy would be to pass 'in' through a clocked D-flop. However, that would increase the latency of the 'in' input, so you may need to modify the overall project to accommodate the extra delay.
 

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