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HELP: HOW TO generate such timing

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arena_yang

arena_yang

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According to the image,
I want to generate the crc_scope according to the soc,eop and val.

As we know,we normally get the falling edge by delaying signals two cycles and then to get the last two-byte pulse scope signal,just as shown in the image below. but how to get the signal for the image above(crc_scope in red)??
 

nval=not val
nval_d1=nval
crc_scope_d1= nvar and not (nval_d1)
crc_scope=crc_scope_da --(have one clock delay)
 

Ignore VAL. Delay SOC (maybe use a shift register) to produce the first Crc_scope pulse. OR it with EOP to produce the second Crc_scope pulse. The result will look like your picture.

If you want Crc_scope to respond to changes in the other signals, then you need to describe your problem better.
 

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