Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Advantage of using Div-2 Frequency Dividers

Status
Not open for further replies.
U

ur72

Newbie level 1
Joined
Jan 30, 2008
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,288
what is advantage of using div

Hello everybody,

I'm wondering if it is desirable to design a frequency divider for a frequency
synthesizer PLL only with 2^n dividers.

Are there any advantages (speed, power dissipation, easy implementation in CMOS,
noise,...) in avoiding digital counters or other non divide-by-two blocks?

Thanks in advance!
Alex
 

Advantages:
High speed: optimize the first divde-by-2, even CML circuit can be used if speed over several GHz;
Low power dissipation: put more current on the first divde-by-2, less on the others; so it's power efficient;
Small size: design the low frequency divide-by-2 with TSPC circuit
Easy implementation: just connect the divide-by-2's
 
Disadvantage:

1. Accumulation of jitter noise in the divider chain
2. 2^N does not always match the VCO to reference frequency ratio
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top