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NEXYS2 Spartan 3E LED issue.

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Rob B

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nexys2

With the most simple Verilog and ISE I can use LEDs 0 to 5 (Balls J14, J15, K15, K14, E17 and P15 respectively on the board).

LEDs 6 and 7 are a different matter (F4 and R4 respectively). I can not get the most basic code to illuminate them although the demo software (VHDL) built on my ISE works, it assigns slide switch values to them.

They are on Bank 3 of the device while the rest are on Bank 1 but that is one of the only differences I can see apart from they share some ball allocations with other footprints. I think the PACE tool takes care of that though as it wouldn't let me assign the alternative ball locations to the nets (I have the correct device selected).

They are all common Cathode according to the schematic ;).

Any ideas appreciated.
 

connect adc to nexys2

I'm not familiar with that board, but . . .

Do you mean that the two signals are connected to the wrong pins, or you don't know were ISE connected them?

Check your "pad summary" report to see if the correct pins were used. It's usually named something like "top_pad.txt".

I've never used PACE. I put my pin numbers into the UCF file or into my HDL as LOC attributes.
 

seven segment nexys2

Looking at the Pad Report, they are being assigned to where I expect and are shown as having the same attributes as the other LED outputs that I chose. The only difference being the bank, which I find suspicious.

I'm using a 500E and F4 and R4 (the problem ones) show as IO and IO/VREF_3 in the datasheet.

This is all just for debug anyway, I'll have to forget about not having my two MSBs and use the seven-segment if I don't find the problem as I haven't started the complicated bit yet!
 

spartan 3e verilog

you are correct with your pin assignments. If you use the provided reference manual it shows all the pin outs for all the peripherals the board contains.

Are you sure its the board and not your code? Have you simulated your code to see if it runs as you require?

As you have already said the demo runs fine so it doesnt look like a board fault.

if i rember correctly i spotted somewhere that F4 and R4 are shared pins. They share with another board peripheral but i cannot think what at this time. If you look at the schematics digilent provide you can check to see what is shares with.


hope it helps
 

nexys 2 jtag cable

The code is really basic, just to test the LEDs but when shifting the LED to LD6 and LD7 (by changing the ball assignments to F4 or R4 from J14, J15, K15, K14, E17, P15 - LEDs 0 to 5 respectively) it doesn't work.

LD6 - F4 - is also connected to E4 pad which is NC on the FG320 package.
LD7 - R4 - is also connected to P4 pad which is NC on the FG320 package.

I can't find it sharing a connection with anything else.

I wasn't trying anything other than reallocating the Verilog output to a different physical one :|.

I'd be better off working on the RS232 as I don't want to read 8k deep arrays from the LEDs anyway :D. Still curious as to why they don't behave as the other ones do though.
 

displays 7 segments spartan 3 pace pin

Just in case your project has some obscure bug, try this Verilog LED blinker. Sorry I don't speak VHDL very well.
The pin and timing constraints are in the HDL, so no need for PACE or UCF.
It runs on my Spartan-3 Starter Kit (with different pin numbers of course). I'm using ISE 9.2.04i.

Code: 
module top (clk, LEDs);
  (* LOC="B8",PERIOD="50 MHz" *) input clk;
  reg [23:0] count = 0;
  (* LOC="R4,F4,P15,E17,K14,K15,J15,J14" *) output reg [7:0] LEDs=0;

  always @ (posedge clk) begin
    count <= count + 1;
    LEDs  <= 1 << count[23:21];
  end
endmodule
 

nexys2 pines

I contacted Digilent and they said that there was no known issue with the ISE9.1i that I'm using.

I should have mentioned that I have been able to get LD7 illuminated, but not when I want!

I'm going to stop worrying about this one now and try to get the other bits working :). I set my memory arrays up and am trying to fill one with ADC data now.

I think I'll start using those LOC attributes, saves re-selecting the device every time I open PACE.

This AVI is better than how I could explain what the above code does... Note that LD7 goes off when LD6 is supposed to be on.
 

spartan 3e tutorial seven segment led schematic

They sure do blink weird! Does LD7 blink off completely, or does it merely get dimmer?

In the pad summary report, be sure LD6 and LD7 are configured as ordinary single-ended drivers such as LVCMOS33 or LVTTL, and not as LVDS or some other inappropriate driver.

You can try viewing the routed chip (usually named something like top.ncd) in FPGA Editor. Look inside the LD6 and LD7 IOBs to be sure they are configured correctly. What you see should match the pad summary report.

Wild guess ----
I assume you are downloading your bitstream through the board's JTAG port. Try temporarily setting the board's Mode jumper to JTAG position, power-cycle the board, and try downloading again. I've seen problems where JTAG download into an already-configured FPGA caused the FPGA design to behave incorrectly, as if the JTAG process didn't fully erase the FPGA.
 

how to use jtag nexys2

I had a look at the top.ncd file with FPGA Editor and LD6/7 seem to be the same as the others, LVCMOS25 and the same drive strengths.

I don't have a Xilinx JTAG cable at present and was loading via the board's USB interface and Digilent's software (no iMPACT usage at the moment then).

I wonder if it does the same if I write the configuration memory instead of just the FPGA? I'll try that later after I struggle along with the other bits...

Finally got round to it...

If I program the configuration ROM it works :).
 

demo nexys2

I've been away for a week . . .

It works from PROM? Great! That sure sounds like the incomplete-JTAG-erase problem that I mentioned in my previous message. With the FPGA running fine from PROM, try downloading the same bitstream from JTAG. I'll bet JTAG works fine this time.

I've seen the incomplete-JTAG-erase problem with Virtex-II and Spartan-3, and now you may be seeing it with Spartan-3E. When I try to explain this problem to Xilinx, it's as futile as talking to a rock. Interestingly, I recently read a Xilinx message explaining how to avoid this problem in Virtex-5, so my suspicion that it's a widespread problem may be correct.
 

vhdl spartan 3e blink led

try:

(* LOC="P4,E4,P16,E16,K14,K15,J15,J14" *) output reg [7:0] LEDs=0;
 

nexys2 spartan 3e 7 seg

i saw the movie and i have a project at school just about the same. i have to display a message on the 4 character and 7 segments display and then make the 8 leds have a dynamical move (they must blink just about the same like in the movie or other random order). i must write this program in VHDl for Spartan 3 kit from XILINGS. Can someone help me too? I would really apreciate it :)
just tell me where i can find similar programs or maybe you can post one for me :)
 

spartan 3e led demo

Hi,
I just got the board a week or so and could not compile simple tutorial execise from Xilinx, LED0,LED1,LED3 and LED4 where fine but got always error when using LED4,LED5, LED6 and LED7...
So looking closely at the schematics for some clue I saw they are written twice but not so in the reference manual and using the other numbers from the schematics it worked.
So they connect as follows:
LED 4 to PIN E16
LED 5 to PIN P16
LED 6 to PIN E4
LED 7 to PIN P4
I hope it works for you as it did for me.
:) :) :)
 

nexys 2 sparten 3e led problem

HI

I just got off a 3 month project where we used the nexys 2 system. I found several minor issues with the documentation (but the boards worked great)

One thing I found was that LED 4,5,6,7 were connected to E16, P16, E4, P4
not E17, P15, F4, R4 you might try rewiring to the above.
 

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