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Verilog:case statement inside always posedge block

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vijay82

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verilog case statement

Is is proper coding convention to use a case statement inside an always @posedge clk block? . Something like

always @(posedge clk or negedge rst_n)
if (rst_n == 1'b0)
<reset logic>
else
case < case variable >
<some logic>
.
.
.
endcase

It works all right, but I haven't seen any professional examples so far.
Thanks for any answers.
 

verilog case syntax

Hello,

yes, you can directly assign new states to case variable, then it's called a Mealy state machine. I prefer it for it's compactness.

Regards,
Frank
 
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