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naming style for identifiers in verilog HDL

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There are two familiar naming styles for identifiers (signal names, port names, module names etc) in verilog HDL.

1. Use lower case letters for all identifiers, for example, rx_flow.

2. Mix lower case letters and upper case letters for all identifiers, for example, RxFlow.

Which style do you use in your design? Why?

I prefer the second style because it is clearer and uses less letters.
 

dear friend,

Putying an underscore is not risky right?

also what to say advantage and disadvantage, its their wish, and easiness.

santu
 

You can read Verilog Coding guidelines of your organisation or client to adopt a proper naming convention
 

most of the organizations prefer the first one
if u want the 2 flopped version of signal say reset its better to name it as reset_2d or reset_dd

I too prefer the same!
naming convention is reqd to understand ur code easily to u and others! otherwise u waste time in understanding itself only!!
 

verilog is a case sensitive HDL...so to avoid having any syntax errors, i'd prefer to use the "all lower case letters with underscores"...(the first example you gave)...

it's important to avoid mixing the cases that may lead to misspelling identifiers...just stick to a unique coding style in all your codes, because mis-typed identifiers may infer an implicit net, without giving a syntax error...and that's a BIG PROBLEM...
 

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