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You need to carefully design the gating circuitry so that runt clocks (shortened clock pulses) are not generated.
If you enable/disable the clock at the wrong time in the clock cycle, you can get clock edges where you don't want or expect them. Obviously, this could cause problems in a synchronous circuit.
Extra effort is also required to make sure that you can still insert scan on the circuitry fed by the gated clock, because all clocks must be controlled from primary inputs. Not hard to do, but if it's not done, you'll lose fault coverage.
Hi
Advantages of clock gating can be stated as,
power saving(most important)
routing effort saving
area saving
Disadvantages,
1.If clock gating is done only with single gate area required is less but care has to be taken for enable signal which should not be afftected by glitches and should be retaind for entire clock cycle.
2.If latched clock gating is used then area and routing can become competitive to original design but in either case power is saved.
"Extra effort is also required to make sure that you can still insert scan on the circuitry fed by the gated clock, because all clocks must be controlled from primary inputs. Not hard to do, but if it's not done, you'll lose fault coverage. "
Synthesis tools and/or internal company scripts can insert a TE (test enable) signal in the clock gating cell or module that bypasses clock gate in the test mode. In short in the test mode : clk in to the module = clk out of module, therefore complete controllability. this is done fairly automatically.
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