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Problem reading generated core in Xilinx ISE 5.1

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crystal

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I have a design, named aaa which consists of ram generated using Core Generator. The ram design generated consists only io ports.

So, i take this design aaa into Xilinx ISE ver 5.1. When i read it at Translate Level, it fails, giving error message saying that it couldn't resolve the module for ram.

How should i read in my files? How does Xilinx ISE5.1 looks for the ram design? It doesn't seemed to be reading it.

Can someone help?
Thanks in advance.
 

Hi!

My experience is that when you generate a core using CoreGen in all case you have to generate the core with some standard pins like ND, CE, RDY.

In fact if you don't , first you will have problem to simulate the core, and second if you don't need this ports you just left them open in your top_design.vhd


Good luck, Bart
 

you must know the generated files how to use it.
every generated file for different goal.
 

Yup, got it fixed already.
I must put all the related files in the same folder in order for it to be read.
 

You must put the edn files generate by coregen in the work folder
 

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