Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to find delay from Xilinx synthesis report and what is combinational path delay

Status
Not open for further replies.
N

nagulapatigirireddy

Newbie level 5
Joined
Nov 11, 2017
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
65
How to find delay from Xilinx synthesis report and what is combinational path delay

Code: 
Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ripple_carry_4_bit.ngr
Top Level Output File Name         : ripple_carry_4_bit
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 15

Cell Usage :
# BELS                             : 8
#      LUT3                        : 8
# FlipFlops/Latches                : 3
#      FD                          : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 14
#      IBUF                        : 9
#      OBUF                        : 5
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s50pq208-5 

 Number of Slices:                       4  out of    768     0%  
 Number of Slice Flip Flops:             3  out of   1536     0%  
 Number of 4 input LUTs:                 8  out of   1536     0%  
 Number of IOs:                         15
 Number of bonded IOBs:                 15  out of    124    12%  
 Number of GCLKs:                        1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 3     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 2.085ns (Maximum Frequency: 479.513MHz)
   Minimum input arrival time before clock: 2.410ns
   Maximum output required time after clock: 7.610ns
   Maximum combinational path delay: 7.824ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 2.085ns (frequency: 479.513MHz)
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
[B]Delay:               2.085ns[/B] (Levels of Logic = 1)
  Source:            p (FF)
  Destination:       q (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: p to q
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.626   0.804  p (p)
     LUT3:I2->O            1   0.479   0.000  fa1/cout1 (c2)
     FD:D                      0.176          q
    ----------------------------------------
    Total                      2.085ns (1.281ns logic, 0.804ns route)
                                       (61.4% logic, 38.6% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 7 / 3
-------------------------------------------------------------------------
[B]Offset:              2.410ns ([/B]Levels of Logic = 2)
  Source:            b<0> (PAD)
  Destination:       p (FF)
  Destination Clock: clk rising

  Data Path: b<0> to p
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.715   1.040  b_0_IBUF (b_0_IBUF)
     LUT3:I0->O            1   0.479   0.000  fa0/cout1 (c1)
     FD:D                      0.176          p
    ----------------------------------------
    Total                      2.410ns (1.370ns logic, 1.040ns route)
                                       (56.8% logic, 43.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
[B]Offset:              7.610ns[/B] (Levels of Logic = 2)
  Source:            r (FF)
  Destination:       cout (PAD)
  Source Clock:      clk rising

  Data Path: r to cout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.626   0.915  r (r)
     LUT3:I1->O            1   0.479   0.681  fa3/cout1 (cout_OBUF)
     OBUF:I->O                 4.909          cout_OBUF (cout)
    ----------------------------------------
    Total                      7.610ns (6.014ns logic, 1.596ns route)
                                       (79.0% logic, 21.0% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 11 / 5
-------------------------------------------------------------------------
[B]Delay:               7.824ns[/B] (Levels of Logic = 3)
  Source:            b<3> (PAD)
  Destination:       cout (PAD)

  Data Path: b<3> to cout
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             2   0.715   1.040  b_3_IBUF (b_3_IBUF)
     LUT3:I0->O            1   0.479   0.681  fa3/cout1 (cout_OBUF)
     OBUF:I->O                 4.909          cout_OBUF (cout)
    ----------------------------------------
    Total                      7.824ns (6.103ns logic, 1.721ns route)
                                       (78.0% logic, 22.0% route)

=========================================================================
CPU : 2.45 / 2.57 s | Elapsed : 3.00 / 3.00 s
 
--> 

Total memory usage is 191504 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
 
Last edited by a moderator:

Altera Quartus II web edition

How to find area, delay, and power of a verilog design?
 

According to synthesis report your circuit has 9 inputs and 5 outputs, which delay are you asking about?
 

FvM said:
According to synthesis report your circuit has 9 inputs and 5 outputs, which delay are you asking about?
Click to expand...

The following code is for 4 bit ripple carry adder. In order to reduce delay, I inserted registers in the critical path. I need delay from 1st input to cout.
In the report there are several delays and offsets. I have bolded the delays and offsets in the report.


Code:
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

module ripple_carry_4_bit(a, b, cin,clk, sum, cout);
input [3:0] a,b;
input cin,clk;
wire c1,c2,c3;
output [3:0] sum;
output  cout;
reg p,q,r;
 
 
full_adder fa0(.a(a[0]), .b(b[0]),.cin(cin), .sum(sum[0]),.cout(c1));
full_adder fa1(.a(a[1]), .b(b[1]), .cin(p), .sum(sum[1]),.cout(c2));
full_adder fa2(.a(a[2]), .b(b[2]), .cin(q), .sum(sum[2]),.cout(c3));
full_adder fa3(.a(a[3]), .b(b[3]), .cin(r), .sum(sum[3]),.cout(cout));
 
always @(posedge clk)
begin
p=c1;
q=c2;
r=c3;
end
 
endmodule
 
Last edited by a moderator:

The following code is for 4 bit ripple carry adder. In order to reduce delay, I inserted registers in the critical path. I need delay from 1st input to cout.
Click to expand...
This breaks the combinational carry chains but actually increases the total cout delay by at least three clock cycles.

If you are trying to achieve maximal throughput, inserting pipeline registers can help. But you'll register all adder output signals, not only the carry.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top