Saltwater
Member level 3
Hi,
Im having trouble with wrapping my head around some array management in "s" verilog.
The case is as follows I have a module getting variables from an array and putting them back altered, on which the array is read out in other parts of my code.
The bog standard version of getting array tables into registers, gives me an error "multiple assignments" for the node putting the variable into the array, even tho this inferred by logic.
The problem arises I think because of the values being read out in other parts of my code. Making a wire for the output value to the array compiles, but has not taken off yet.
My question is twofold, is there syntax for calling an overhead array in verilog like "module.array[index]" or "module.array[vector][index]"?
also, is this possible to have wires from this array, when another part is setting the value? or do I need to lock the array?
Regards,
Im having trouble with wrapping my head around some array management in "s" verilog.
The case is as follows I have a module getting variables from an array and putting them back altered, on which the array is read out in other parts of my code.
The bog standard version of getting array tables into registers, gives me an error "multiple assignments" for the node putting the variable into the array, even tho this inferred by logic.
The problem arises I think because of the values being read out in other parts of my code. Making a wire for the output value to the array compiles, but has not taken off yet.
My question is twofold, is there syntax for calling an overhead array in verilog like "module.array[index]" or "module.array[vector][index]"?
also, is this possible to have wires from this array, when another part is setting the value? or do I need to lock the array?
Regards,