rmachado
Member level 2
Hi everyone,
I have a very basic I2C slave ASIC with a bank of registers that I am currently testing. The ASIC was produced just to test the I2C IP (to make sure the design flow was correct and that the IP was ready to be used in more complex projects). According to the simulations and tests performed before tape-out, the ASIC should always work, but in reality... It only works in a specific scenario.
In I2C, when you want to write a zero on the SCL and SDA lines you have to force them low, but when you want to write a one, you just release the line and let the pull-up do the job.
The problem is that the I2C ASIC that I have only works properly if both transitions on the SCL and SDA lines are forced. If I force both rising and falling transitions on the SDA and SCL lines (in bit bang mode), the ASIC works as it should. Although, if I only force the falling transitions and let the pull-up control the rising transitions, then the ASIC does not work properly.
My guess is that this is probably some issues with parasitics. I started the tests with 10k pull-up resistors and the ASIC was not working properly, so I repeat the tests with a lower resistance (4.7k) to increase the pull-up strength but the ASIC still does not work as it should.
I identify some strange scenarios during my tests. Following are some images with the error cases and an explanation of what I think is the problem. (the SCL signal is represented in yellow and the SDA in blue)
The problem can be seen in 8th falling edge of the SCL signal. Both SCL and SDA go low at the same time which can lead to a start condition, restarting the system. The problem is, the only way for the SDA go low in that scenario is if the Slave is pulling the line low since the master is still sending the slave addr data packet. imideatly after a spike can be seen, this corresponds to the time where the master is forcing the line low to send the read/write bit. Also in this example, it can be seen that the SDA line is held low at the end of the communication. This is for sure being done by the ASIC slave and I really don't know why because the state machine of the I2C slave only forces the line low when it needs to send an ACK (and that only ocurs for one I2C clock cycle) or when it is in write to master mode (which is impossible because for that a one had to be sent on the last bit of the slave address paket).
I also have a scenario were the slave address (0x27) is sent correctly but still I receive a NACK from the slave.
Any idea on the possible route of the problem, or any idea on tests that I could run to try to learn more about the problem?
Thanks in advance
I have a very basic I2C slave ASIC with a bank of registers that I am currently testing. The ASIC was produced just to test the I2C IP (to make sure the design flow was correct and that the IP was ready to be used in more complex projects). According to the simulations and tests performed before tape-out, the ASIC should always work, but in reality... It only works in a specific scenario.
In I2C, when you want to write a zero on the SCL and SDA lines you have to force them low, but when you want to write a one, you just release the line and let the pull-up do the job.
The problem is that the I2C ASIC that I have only works properly if both transitions on the SCL and SDA lines are forced. If I force both rising and falling transitions on the SDA and SCL lines (in bit bang mode), the ASIC works as it should. Although, if I only force the falling transitions and let the pull-up control the rising transitions, then the ASIC does not work properly.
My guess is that this is probably some issues with parasitics. I started the tests with 10k pull-up resistors and the ASIC was not working properly, so I repeat the tests with a lower resistance (4.7k) to increase the pull-up strength but the ASIC still does not work as it should.
I identify some strange scenarios during my tests. Following are some images with the error cases and an explanation of what I think is the problem. (the SCL signal is represented in yellow and the SDA in blue)
The problem can be seen in 8th falling edge of the SCL signal. Both SCL and SDA go low at the same time which can lead to a start condition, restarting the system. The problem is, the only way for the SDA go low in that scenario is if the Slave is pulling the line low since the master is still sending the slave addr data packet. imideatly after a spike can be seen, this corresponds to the time where the master is forcing the line low to send the read/write bit. Also in this example, it can be seen that the SDA line is held low at the end of the communication. This is for sure being done by the ASIC slave and I really don't know why because the state machine of the I2C slave only forces the line low when it needs to send an ACK (and that only ocurs for one I2C clock cycle) or when it is in write to master mode (which is impossible because for that a one had to be sent on the last bit of the slave address paket).
I also have a scenario were the slave address (0x27) is sent correctly but still I receive a NACK from the slave.
Any idea on the possible route of the problem, or any idea on tests that I could run to try to learn more about the problem?
Thanks in advance