fpga93
Newbie level 4
Hi all,
I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA has just 48 pins (1 I/O ) bank that supports I/O standards upto 3.3 V ,rest all pins among the other 280+ pins are supporting standards only upto 1.8 V .
One of the 3.3V peripherals itself have around 60-70 I/O pins , using a voltage translator chips might introduce skew between the signals...as voltage translator chips generally only support max upto 32 signals.
If anyone can suggest a workaround to effectively use Cyclone 10 GX smoothly.
Thanks,
fpga993
I have recently encountered a problem while working with a design that has alot (4 to 5) 3.3 v I/O peripherals to be interfaced with Cyclone 10 GX FPGA. The design challenge is the FPGA has just 48 pins (1 I/O ) bank that supports I/O standards upto 3.3 V ,rest all pins among the other 280+ pins are supporting standards only upto 1.8 V .
One of the 3.3V peripherals itself have around 60-70 I/O pins , using a voltage translator chips might introduce skew between the signals...as voltage translator chips generally only support max upto 32 signals.
If anyone can suggest a workaround to effectively use Cyclone 10 GX smoothly.
Thanks,
fpga993