biju4u90
Full Member level 3
In the case of ASIC, there are many ways to fix set up and hold like upsizing/downsizing cells, buffering/removing buffer, skew insertion, LVT/HVT cells etc. What about FPGA? I see many articles referring to fixing setup and hold violations in ASIC. But I don't see much help for FPGA. How can I deal with setup and hold violations in FPGA??