rrucha
Member level 3
Hello,
I have the auto generated CRC parallel verilog code for muti-bit data stream. I even wrote a testbench to check the CRC. Now I want to write a testbench that injects random errors and detects it. How can i do that in verilog?
I have the auto generated CRC parallel verilog code for muti-bit data stream. I even wrote a testbench to check the CRC. Now I want to write a testbench that injects random errors and detects it. How can i do that in verilog?