barry
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I've finally bitten the bullet and crossed over from VHDL to the dark world of System Verilog. I've got a testbench that causes Questasim (Modelsim) to throw the following error:
# ** Error: (vlog-13069) C:/AirMattress/ARIN_Main/tb_top_beam.sv(571): near "[": syntax error, unexpected '[', expecting ';'.
Here's the piece of code that causes the error; it's the line with "slice=" that causes the problem. This looks perfectly ok to me; what am I doing wrong?
- - - Updated - - -
Update: if I pull the elements out separately, it works fine:
# ** Error: (vlog-13069) C:/AirMattress/ARIN_Main/tb_top_beam.sv(571): near "[": syntax error, unexpected '[', expecting ';'.
Here's the piece of code that causes the error; it's the line with "slice=" that causes the problem. This looks perfectly ok to me; what am I doing wrong?
Code:
logic [39:0] bt1[511:0];
logic [39:0] bt2[511:0];
logic [39:0] bt3[511:0];
logic [39:0] bt4[511:0];
logic [4:0]slice;
logic [39:0]row;
initial
begin
$display (" ");
$display (" ");
$readmemh("beam_table1.txt",bt1);
$readmemh("beam_table2.txt",bt2);
$readmemh("beam_table3.txt",bt3);
$readmemh("beam_table4.txt",bt4);
#10ms;
slice=bt1[12:8][1];
- - - Updated - - -
Update: if I pull the elements out separately, it works fine:
Code:
logic [39:0] bt1[0:511];
logic [39:0] bt2[0:511];
logic [39:0] bt3[0:511];
logic [39:0] bt4[0:511];
logic [4:0]slice;
logic [39:0]row;
initial
begin
$display (" ");
$display (" ");
$readmemh("beam_table1.txt",bt1);
$readmemh("beam_table2.txt",bt2);
$readmemh("beam_table3.txt",bt3);
$readmemh("beam_table4.txt",bt4);
#10ms;
row=bt1[1];
slice=row[12:8];