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Does Solid State Marx Generators actually work?

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Interesting experiment, interesting results.
I have a half-baked theory that your Stage3 Charge driver is malfunctioning. Refer again to my concern about exceeding Gnd1-Gnd2 isolation Max voltage.

That would possibly explain some of your observations.
 

I summoned the strength to solder a couple of current sense resistors to stage 4 and do some measurements. It seems to me that the cap is discharging instantly through the diode, what do you think?

current-1.png

If it does, why does it do it? I tried with faster, slower, bigger diodes and increase the time between Qc/Qd turns ON/OFF but none of that helped. An finally where does it discharge to?
 

I soldered some more sense resistors, and it seems it paid off. I believe I found the unwanted discharge path for C4 and C3

marx-26.png

As you remember, stage3 and stage4 are the malfunctioning stages in this configuration. When all caps get charged, ONLY Qdischarge4 is triggered (for debugging purposes).

Now how can the diodes D3 and D4 conduct?

I believe it is because the caps reverse polarity, here is C3 when it discharges, as you can see it reverses polarity:
Note 200V/DIV
C3-discharge.png

How does Qd2 and Qd3 conduct when they are active OFF?

Well I found some noise on Qd2 and Qd3 gates that could explain that. (Qd4 is ON, Qd5/1/2 are OFF - and all those signals are noise free)
Qd2 Vge
Qd2-Vg.png
Qd3 Vge
Qd3-Vg.png

BUT WHY it does all happen when Qd4 is turned ON? I haven't the foggiest clue yet.
 

I don't get it.

You are seriously violating the Absolute Maximum rating of Gnd - Gnd voltage tolerance of your driver ICs, and yet are not focusing on how to resolve an obvious problem.
Why is this ? How are you so sure that this exceeding of max rated voltage is not causing any problems ?
 

I don't get it.

You are seriously violating the Absolute Maximum rating of Gnd - Gnd voltage tolerance of your driver ICs, and yet are not focusing on how to resolve an obvious problem.
Why is this ? How are you so sure that this exceeding of max rated voltage is not causing any problems ?

I don't get it too....that is - what you are saying "Gnd voltage tolerance of your driver ICs"? What do you mean by that? And why aren't you on holiday like everybody else? You don't have an auto-camper?
 

I don't get it too....that is - what you are saying "Gnd voltage tolerance of your driver ICs"? What do you mean by that? And why aren't you on holiday like everybody else? You don't have an auto-camper?

Is that a serious question ? Really ?
Based on the spec sheets of your driver IC, the max tolerable voltage difference between GND1 and GND2 is 1200v before breakdown and catastrophic failure, presumably.

Since your circuit exceeds these voltage limits, especially during discharge in stage 3 and beyond, I have repeatedly pointed out to you to check this issue.

I live in India. We have different 'holidays'. We don't auto-camp. The land itself is our camp.

Check your Absolute Maximum Ratings of your driver IC's. Get better ones, or cascade them or something. But that spec looks serious to me.
 

Since your circuit exceeds these voltage limits, especially during discharge in stage 3 and beyond, I have repeatedly pointed out to you to check this issue.

Just to bust your theory I have measured the potential difference between GND1 and GND2 in stage3 and the reading was 200V and that is with 600V supply.

You have to think of the chain of events, it starts with Qd4 turning ON and that starts a chain reaction. My theory now; it's the caps somehow.

I live in India. We have different 'holidays'. We don't auto-camp. The land itself is our camp.

And isn't that the perfect opportunity to be a local trendsetter? I have this one on my build list, maybe you could do the same with a TATA bus? You would make the news and hobnob with all the popular cricket celebs.

- - - Updated - - -

I tried something new...

I removed C4, and it did nothing, so I put it back.

I removed D4, and C3 charged up, and didn't discharge instantly, and the gate Qd3 and Qd2 were without any noise. So it seems without D4 stages 5+1+2+3 are working properly.

But without D4 all stages will not discharge into the load. So either I have to figure out why D4 is problematic, or maybe use a MOSFET instead of D4?
 

I have a new theory as to what is wrong, is there an EE in the house that could confirm it?

My new theory is that it's paracitics, so I added some stray inductance and capcitance to the simulation and it shows what I'm somewhat measuring. in this case I have 5 (c1-5) caps all charged up to 600V each, so I would expect 3KV output once all the Td's are ON, but here allmost 50% is lost due to paracitics.

Screenshot from 2019-07-15 17-08-39.png
 

I have a new theory as to what is wrong, is there an EE in the house that could confirm it?

My new theory is that it's paracitics, so I added some stray inductance and capcitance to the simulation and it shows what I'm somewhat measuring. in this case I have 5 (c1-5) caps all charged up to 600V each, so I would expect 3KV output once all the Td's are ON, but here allmost 50% is lost due to paracitics.

View attachment 154419

Interesting.

I think it's time you posted some pics of your setup. Maybe there are some other obvious issues you have not considered as yet which might come to light with pics.
 

Parasitic capacitances surely matter, surprising that you start now to think about it. 2 x 2nF however isn't but a shot in the dark and should be justified with datasheet specs and measurements. Are we still dealing with IGW15T120 IGBT switches? They have < 100 pF output capacitance, PCB capacitances per stage should be considerably lower.

No idea about gate driver and DC/DC parasitic capacitances. You have the circuit at your fingertips and can easily verify capacitance assumptions.
 

Interesting.

I think it's time you posted some pics of your setup. Maybe there are some other obvious issues you have not considered as yet which might come to light with pics.

I just dismantled it, and ordered new pcb's, so when I assemble it again. In the meantime you can feast your eyes on the new layout, it's 66% narrower and then I won't stack it but rather do side-by-side to minimize distance.

Screenshot from 2019-07-17 19-36-20.png

- - - Updated - - -

Parasitic capacitances surely matter, surprising that you start now to think about it.

I was living on the hope that it wouldn't be an issue, especially with only 20KHz. And if it was an issue it would be seen on the result, as I know no authorized method to estimate, quantify and measure parasitics.

2 x 2nF however isn't but a shot in the dark and should be justified with datasheet specs and measurements.

Not completely in the dark, I started with low values, and then I increased them until the simulation would show something I would recognize from the measurements.

Are we still dealing with IGW15T120 IGBT switches? They have < 100 pF output capacitance, PCB capacitances per stage should be considerably lower.

Yes but the 25A version STGW25H120F2, they were on sale from Arrow at ¢60 piece

No idea about gate driver and DC/DC parasitic capacitances. You have the circuit at your fingertips and can easily verify capacitance assumptions.

I'm not experiencing any gate driving issues, the signals are clean.
 

What 20khz are you referring to? And what is that yellow line on your pcb between drivers pads?
 

What 20khz are you referring to? And what is that yellow line on your pcb between drivers pads?

20khz would be the maximum expected switching frequency, but for now I'm testing at one pulse only.

The yellow line is a creepage cutout, i.e. the line will be milled through.
 

Not completely in the dark, I started with low values, and then I increased them until the simulation would show something I would recognize from the measurements.
Sure, if parasitic capacitance causes the voltage drop, it must have a similar value. But is the capacitance value realistic?

Capacitance can be measured with LCR meter or various homemade circuits. Parasitic capacitance of the shown PCB is surely low, I guess not more than a few 10 pF. Unknown point is however the isolated gate driver supply.
 

Interesting.
My rudimentary analysis indicates that each of your caps would have to charge through your load, in sequence starting with your last stage and working backwards to the 1st stage. That would take many mS to complete.

Of course I'm just a noob, so could be totally wrong.
 

Interesting.
My rudimentary analysis indicates that each of your caps would have to charge through your load, in sequence starting with your last stage and working backwards to the 1st stage. That would take many mS to complete.

Of course I'm just a noob, so could be totally wrong.

What do you mean by "would have"?

noob at giving expert advise? or noob at EE? I hope you are not giving expert advise without proper edabord certification and authorization ;-)
 

What do you mean by "would have"?

noob at giving expert advise? or noob at EE? I hope you are not giving expert advise without proper edabord certification and authorization ;-)

Ah ha. My mistake in transcribing your circuit into SPICE. Ignore my previous post :smile:
 

When you switch all the capacitors to join in series, their voltage differentials add up to extreme levels that can destroy components.

Node voltages change instantly as transistors are turned Off or On. Besides that, polarities can be positive or negative, depending on where you provide at low-ohm path.

It is easier to manage the first half of the cycle, that is, to connect each capacitor between supply and ground.
Then the second half of the cycle connects all capacitors in series. Notice that when you provide the most positive (final) capacitor a low-ohm path to ground (via reservoir capacitor or load), you instantly create extreme negative polarity at the first capacitor. (It happens even in a system running from a positive supply.)

This makes it difficult to create an effective switching scheme.

In simulations I've looked for a way to charge capacitors in parallel, then connect them in series to a load. It becomes clear that it's essential, at each node, (1) to correctly choose an N or P transistor, and (2) apply bias voltages at levels that turn them completely On and Off.

Here's my simulation which appears to work properly. Three capacitors wired in series with the load. Capacitors are charged one at a time in rotation.

3-cap stack chg'd in rotation 3 half-bri 6 transis 4 clks 100VDC supply.png

It requires a more complicated clocking scheme. The middle capacitor requires a PNP and NPN.

At first it appeared to make sense to use NPN type to connect the first capacitor to ground. However as the capacitors charge, a rogue current flows at times, up from 0V ground through the NPN. By changing to a PNP, no current flows upward. Thus the first capacitor has PNP above and below.

Likewise it seemed common sense to use a PNP type to connect supply voltage to the final capacitor. But again a rogue current flows up into the supply. An NPN type is required. Thus the last capacitor has NPN above and below.
 

Hi BradtheRad,

First of all a huge thank you for taking the time to make this elaborate analysis of the circuit. You should write a paper on it and publish it.

When you switch all the capacitors to join in series, their voltage differentials add up to extreme levels that can destroy components.

Node voltages change instantly as transistors are turned Off or On. Besides that, polarities can be positive or negative, depending on where you provide at low-ohm path.

It is easier to manage the first half of the cycle, that is, to connect each capacitor between supply and ground.
Then the second half of the cycle connects all capacitors in series. Notice that when you provide the most positive (final) capacitor a low-ohm path to ground (via reservoir capacitor or load), you instantly create extreme negative polarity at the first capacitor. (It happens even in a system running from a positive supply.)

This makes it difficult to create an effective switching scheme.

I'm pleased to learn that your analysis confirms my observations and theory of rouge currents, polarity/node voltage change. I personally could not provoke my simulation to produce neither and I would really like to take a closer look t it in a simulation environment.

I also highly appreciate your alternative topology proposal and FYI I have tried sequential charging in the present physical circuit, but that didn't unfortunately change anything.

As an aber dabei, I would be bit reluctant to try your topology because I see some limitations for my personal application e.g. using available BJT's, the high voltage ones I have seen are limited to below 200mA or something like that. I'm sure it could be adapted to IGBT's but then the sequential charging would perhaps reduce the firing rate and so on etc. you know what I mean. All in all what I'm trying to say is that purported simplicity of the MG at hand is out the window, and I might as well try using IGBT's in series with whatever can of worm that opens. I'm sure it's not so simple to make the dynamic voltage balancing that is required for serializing. I hope you understand what I'm saying, I'm not in any way dismissing your effort, results or conclusions, it's just a practical consideration.
 

By trying a while longer I managed to make a workable simulation (in theory). Although this thread has the name Marx generator, the topology (switching capacitors between H-bridges) appears to be a circuit which I first saw named a Nakagome charge pump. Thus the name on my screenshot.

3-cap Nakagome charge pump supply 100VDC load gets 380VDC.png

There are no rogue or backward current flows. It only needs one clock. Nmos seems to work in the right places. Similarly Pmos is used in the right places. Since high voltage is present, mosfets are not the right device to use. However I used them instead of transistors since numerous bias resistors makes a schematic crowded and hard to grasp.

I can't be certain my design is optimal. To confirm whether it is, it helps to start the layout by using analog switches (a 'cheat' shortcut). Apply clock signals that make the simulation perform properly. Then go through the switches one at a time, replacing each with a transistor. Test whether an NPN works, or if not, a PNP.

To provide bias there may be a suitable node which produces the right voltage at the right time. It may be a supply wire, or a ground wire, or another leg of the same transistor. Sometimes a transistor is not needed because a diode can do the job.

An alternate switching device might be SCR's. They continue to conduct as long as capacitors are charging. As charge current declines to zero, SCR's turn off. This simplifies clocking.
 

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